skyzh / mips-cpu
💻 A 5-stage pipeline MIPS CPU implementation in Verilog.
☆28Updated 4 years ago
Alternatives and similar repositories for mips-cpu:
Users that are interested in mips-cpu are comparing it to the libraries listed below
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆39Updated 7 years ago
- A softcore microprocessor of MIPS32 architecture.☆39Updated 9 months ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆34Updated 3 years ago
- MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support☆106Updated 5 years ago
- 基于龙芯FPGA开发板的计算机综合系统实验☆25Updated 6 years ago
- 中国科 学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session☆32Updated 7 years ago
- Computer System Project for Loongson FPGA Board in 2017☆52Updated 6 years ago
- ☆34Updated 5 years ago
- 奋战一学期,造台计算机(编译出的bit文件在release中,可以直接食用)☆126Updated 5 years ago
- 计算机组成原理课程32位监控程序☆48Updated 4 years ago
- 💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…☆201Updated 4 years ago
- Uranus MIPS processor by MaxXing & USTB NSCSCC team☆38Updated 5 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆47Updated last year
- SoC for CQU Dual Issue Machine☆12Updated 2 years ago
- Naïve MIPS32 SoC implementation☆113Updated 4 years ago
- A MIPS CPU implemented in Verilog☆67Updated 7 years ago
- riscv32i-cpu☆19Updated 4 years ago
- nscscc2018☆26Updated 6 years ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆170Updated 3 years ago
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆72Updated 5 years ago
- 龙芯杯21个人赛作品☆34Updated 3 years ago
- CQU Dual Issue Machine☆35Updated 9 months ago
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆42Updated 4 years ago
- Recommended coding standard of Verilog and SystemVerilog.☆34Updated 3 years ago
- NUDT 高级体系结构实验☆34Updated 6 months ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆48Updated 4 months ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆38Updated last year
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago
- 为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助☆122Updated 4 years ago
- 💻 A 5-stage pipeline MIPS CPU design in Haskell.☆36Updated 4 years ago