Alternatives and similar repositories for computer-systems-ucas

Users that are interested in computer-systems-ucas are comparing it to the libraries listed below

• nscscc2019ucas / nscscc2019ucas
  ☆34Updated 5 years ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆40Updated 11 months ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆43Updated 4 years ago
• xyongcn / LoongsonCsprj2017
  Computer System Project for Loongson FPGA Board in 2017
  ☆52Updated 7 years ago
• ustb-owl / Uranus
  Uranus MIPS processor by MaxXing & USTB NSCSCC team
  ☆38Updated 5 years ago
• Corle-hyz / UCAS-COD-Lab
  中国科学院大学(UCAS)2020年春季学期计算机组成原理实验课作业
  ☆17Updated 3 years ago
• nicolaswilde / UCAS-Advanced-Computer-Architecture-OpenROAD-flow
  中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程
  ☆29Updated 5 years ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆26Updated 6 years ago
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆127Updated 4 years ago
• Rzfly / simple_riscv_soft_core
  This is a simple Risc-v core for software simulation on FPGA.
  ☆8Updated 3 years ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆29Updated 2 years ago
• bit-mips / cpu
  MIPS CPU
  ☆14Updated 4 years ago
• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆115Updated 5 years ago
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆34Updated 5 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• yuhanzhu612 / OSCPU
  我的一生一芯项目
  ☆16Updated 3 years ago
• cebarobot / UCAS-CALab-mycpu_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9
  ☆28Updated 3 years ago
• OSCPU / yosys-sta
  ☆72Updated 2 months ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆36Updated 3 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 7 months ago
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆106Updated 6 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆137Updated last year
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆40Updated 7 years ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆82Updated 5 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆131Updated last year
• OSCPU / ysyxSoC
  ☆86Updated last month
• cebarobot / UCAS-Computer-Architecture-Lab
  计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集
  ☆18Updated 3 years ago
• fox6666 / RISC_V-pipeline
  基于RISC_V32I指令集架构的五级流水CPU
  ☆15Updated 5 years ago
• Trinkle23897 / mips32-cpu
  奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）
  ☆128Updated 5 years ago
• yang-le / riscv_cpu
  a simple riscv cpu
  ☆23Updated 2 years ago