Alternatives and similar repositories for supervisor-rv:

Users that are interested in supervisor-rv are comparing it to the libraries listed below

• z4yx / supervisor-mips32
  计算机组成原理课程32位监控程序
  ☆48Updated 4 years ago
• thu-cs-lab / thinpad_top
  Project template for Artix-7 based Thinpad board
  ☆45Updated last year
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆106Updated 5 years ago
• Trinkle23897 / mips32-cpu
  奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）
  ☆126Updated 5 years ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆34Updated 3 years ago
• decaf-lang / minidecaf
  The MiniDecaf compilers.
  ☆67Updated 4 years ago
• xyongcn / LoongsonCsprj2017
  Computer System Project for Loongson FPGA Board in 2017
  ☆52Updated 6 years ago
• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆113Updated 4 years ago
• AlwenXXD / nscscc2021
  龙芯杯21个人赛作品
  ☆34Updated 3 years ago
• MashPlant / computational_graphics_2019
  THU Computational Graphics course projects, grade A+.
  ☆36Updated 2 years ago
• TrivialCompiler / TrivialCompiler
  A toy compiler written in C++17 that translates SysY (a C-like toy language) into ARM-v7a assembly.
  ☆138Updated 3 years ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆39Updated 8 months ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆76Updated last year
• jiegec / Projects
  A summary of my projects
  ☆47Updated this week
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆38Updated last year
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆122Updated 4 years ago
• YAVGroup / Verilog-OJ
  Online judge server for Verilog | verilogoj.ustc.edu.cn
  ☆77Updated 8 months ago
• nscscc2019ucas / nscscc2019ucas
  ☆34Updated 5 years ago
• oscourse-tsinghua / LoongsonCsprj2017-manual
  基于龙芯FPGA开发板的计算机综合系统实验
  ☆25Updated 6 years ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆42Updated 4 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆47Updated last year
• hitwh-nscscc / simple-5stage-pipeline-MIPS-imple
  和我一步一步实现一个最简单的、带数据前推及流水线暂停的32位静态五级流水MIPS
  ☆83Updated 4 years ago
• jhdjames37 / RISC-V-CPU-simple
  清华大学《计算机组成原理》大实验——五级流水线 RISC-V 处理器。「奋战三星期，造台计算机」
  ☆13Updated 2 years ago
• LearningOS / rCore-Tutorial-Code-2023S
  Let's write an OS which can run on RISC-V in Rust from scratch!
  ☆16Updated last year
• loongson-education / nscscc-wiki
  NSCSCC 信息整合
  ☆234Updated 4 years ago
• FDUCSLG / ICS-2021Spring-FDU
  Introduction to Computer Systems (II), Spring 2021
  ☆50Updated 3 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆128Updated last year
• MashPlant / Router-Lab
  THU network principle project.
  ☆18Updated 5 years ago
• z4yx / ucore-thumips
  uCore MIPS32 porting
  ☆18Updated 5 years ago
• skyzh / RISCV-Simulator
  💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…
  ☆201Updated 4 years ago