Alternatives and similar repositories for mips-simulator:

Users that are interested in mips-simulator are comparing it to the libraries listed below

• imkiva / valheim
  Just for fun riscv64 emulator, which boots the Linux.
  ☆41Updated 2 years ago
• losfair / Violet
  Superscalar RISC-V processor written in Clash.
  ☆34Updated 2 years ago
• oscourse-tsinghua / LoongsonCsprj2017-manual
  基于龙芯FPGA开发板的计算机综合系统实验
  ☆25Updated 6 years ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• dramforever / finlog
  Compiling finite generators to digital logic. WIP
  ☆14Updated 4 years ago
• pku-minic / first-step-rs
  Take your first step in writing a compiler. Implemented in Rust.
  ☆15Updated 2 years ago
• Harry-Chen / rust-mips
  Rust library for low-level abstraction of MIPS processors
  ☆31Updated 4 years ago
• rcore-os / x86-smpboot
  Booting multi-processors on x86 bare-metal.
  ☆11Updated 3 years ago
• typekernel / typekernel
  Warning: 🕳 ahead!
  ☆16Updated 5 years ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 3 years ago
• trackoor / AwesomePL
  A Collection of Papers & Notes in Programming Language & Formal Verification
  ☆17Updated 2 years ago
• nbdd0121 / r2vm
  Rust RISC-V Virtual Machine
  ☆97Updated 5 months ago
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆30Updated 2 years ago
• wangrunji0408 / rjrouter
  [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)
  ☆14Updated 4 years ago
• z4yx / vivado-docker
  Dockerfile with Vivado for CI
  ☆28Updated 5 years ago
• MashPlant / lalr1
  An LALR1(1)/LL(1) parser generator in Rust, for multiple languages.
  ☆48Updated 3 years ago
• oscourse-tsinghua / cpu-testcase
  Test cases for MIPS CPU implementation
  ☆12Updated 5 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• rcore-os / trapframe-rs
  Handle TrapFrame across kernel and user space on multiple ISAs.
  ☆33Updated 9 months ago
• skyzh / mips-cpu
  💻 A 5-stage pipeline MIPS CPU implementation in Verilog.
  ☆31Updated 4 years ago
• rcore-os / rcore-user
  User programs for rCore OS
  ☆18Updated 2 years ago
• SchrodingerZhu / reussir-lang
  The Reussir Programming Language. Reuse Analysis in MLIR and Rust. Functional programming meets performance.
  ☆16Updated 3 weeks ago
• SchrodingerZhu / VNMCC
  Very Naive MIPS CPU using Clash
  ☆29Updated 3 years ago
• rcore-os / aCore
  Asynchronous OS kernel written in Rust.
  ☆34Updated 4 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• ring00 / bbl-ucore
  uCore OS Labs on Berkeley bootloader
  ☆39Updated 7 years ago
• shady831213 / terminus
  A riscv isa simulator in rust.
  ☆64Updated last year
• lynzrand / chigusa
  A C0 compiler for homework | C0 编译器 | 北航软院编译原理大作业
  ☆30Updated 4 years ago
• AD1024 / veripy
  Python3 auto-active verification library (migrated to an Intel project)
  ☆25Updated 3 years ago
• Inokinoki / softfpu-rs
  A WIP Float32 soft FPU implementation
  ☆22Updated 3 years ago