skordal / sha256Links
A simple SHA-256 implementation in VHDL
☆23Updated 7 years ago
Alternatives and similar repositories for sha256
Users that are interested in sha256 are comparing it to the libraries listed below
Sorting:
- A litecoin scrypt miner implemented with FPGA on-chip memory.☆291Updated 11 years ago
- A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open d…☆176Updated 3 years ago
- SHA256 in (System-) Verilog / Open Source FPGA Miner☆83Updated 7 years ago
- A Bitcoin miner for the Zynq chip utilizing the Zedboard.☆107Updated 2 years ago
- Bitcoin miner for Xilinx FPGAs☆99Updated 12 years ago
- An open source FPGA miner for Blakecoin☆52Updated 11 years ago
- Public repository for PicoEVB (Xilinx Artix XC7A50T based)☆263Updated last week
- Cryptonight Monero Verilog code for ASIC☆20Updated 7 years ago
- AES-128 hardware implementation☆33Updated 5 years ago
- A utility for Composing FPGA designs from Peripherals☆185Updated 11 months ago
- ☆63Updated 6 years ago
- Hardware implementation of the SHA-256 cryptographic hash function☆364Updated 4 months ago
- VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin☆63Updated 7 years ago
- A 32-bit Microcontroller featuring a RISC-V core☆158Updated 7 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆41Updated 9 years ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆97Updated 3 years ago
- Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog☆200Updated 7 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Updated 2 years ago
- SHA256 hardware accelerator, synthesized for and mapped on the Zynq core of the Zybo board by Digilent☆27Updated 7 years ago
- ☆113Updated 8 months ago
- Collection of open-source peripherals in Verilog☆183Updated 3 years ago
- FreeRTOS for RISC-V☆27Updated 6 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆100Updated 6 years ago
- A wishbone controlled scope for FPGA's