Alternatives and similar repositories for moneroasic:

Users that are interested in moneroasic are comparing it to the libraries listed below

• unixb0y / SystemVerilogSHA256
  SHA256 in (System-) Verilog / Open Source FPGA Miner
  ☆78Updated 7 years ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆35Updated last year
• secworks / sha512
  Verilog implementation of the SHA-512 hash function.
  ☆38Updated 3 years ago
• raya4213 / VerilogCodeECC
  Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field
  ☆22Updated 8 years ago
• ZcashFoundation / zcash-fpga
  Zcash FPGA acceleration engine
  ☆121Updated 4 years ago
• fatestudio / RSA4096
  4096bit RSA project, with verilog code, python test code, etc
  ☆45Updated 5 years ago
• Goshik92 / SHA256Hasher
  SHA-256 IP core for ZedBoard (Zynq SoC)
  ☆31Updated 6 years ago
• scarv / xcrypto
  XCrypto: a cryptographic ISE for RISC-V
  ☆92Updated 2 years ago
• d953i / SQRL_FK33
  SQRL FK33 board files, example designs and scripts.
  ☆17Updated 2 years ago
• teknohog / Xilinx-Serial-Miner
  Bitcoin miner for Xilinx FPGAs
  ☆97Updated 11 years ago
• kramble / FPGA-Blakecoin-Miner
  An open source FPGA miner for Blakecoin
  ☆51Updated 10 years ago
• 0x2fed / FPGA-GroestlCoin-Miner
  An Open Source FPGA GroestlCoin Miner
  ☆10Updated 7 years ago
• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆35Updated 4 years ago
• pnvamshi / Hardware-Implementation-of-AES-Verilog
  Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog
  ☆39Updated 7 years ago
• ljhsiun2 / EllipticCurves_SystemVerilog
  Elgamal's over Elliptic Curves
  ☆19Updated 6 years ago
• altASIC / Open-CryptoNight-ASIC
  Open source hardware implementation of classic CryptoNight
  ☆37Updated last year
• secworks / modexp
  Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.
  ☆17Updated 4 years ago
• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆32Updated 7 years ago
• KULeuven-COSIC / CryptoNightHaven-FPGA-miner
  Mining CryptoNight Haven on the Varium C1100
  ☆10Updated 3 years ago
• fpgaminer / Open-Source-FPGA-Bitcoin-Miner
  A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open d…
  ☆173Updated 3 years ago
• SpinalHDL / SpinalCrypto
  SpinalHDL - Cryptography libraries
  ☆52Updated 8 months ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆38Updated 5 years ago
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆64Updated 2 years ago
• fatestudio / RSA4096_NEW
  ☆13Updated 9 years ago
• mih0 / FPGA_Mining_AWS
  Example verilog / miner for crypto mining using AWS F1 instances
  ☆30Updated 6 years ago
• kgpai94 / ECC-Encryption-System
  This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…
  ☆31Updated 6 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 4 years ago
• momalab / CoPHEE
  CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
  ☆31Updated last year
• scarv / scarv
  SCARV: a side-channel hardened RISC-V platform
  ☆18Updated 4 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆44Updated 2 years ago