stremovsky / moneroasicLinks
Cryptonight Monero Verilog code for ASIC
☆20Updated 7 years ago
Alternatives and similar repositories for moneroasic
Users that are interested in moneroasic are comparing it to the libraries listed below
Sorting:
- SHA256 in (System-) Verilog / Open Source FPGA Miner☆80Updated 7 years ago
- Verilog implementation of the SHA-512 hash function.☆39Updated 5 months ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆39Updated last year
- Hardware implementation of the SHA-256 cryptographic hash function☆353Updated last month
- SQRL FK33 board files, example designs and scripts.☆17Updated 2 years ago
- XCrypto: a cryptographic ISE for RISC-V☆93Updated 2 years ago
- Elgamal's over Elliptic Curves☆19Updated 6 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open d…☆175Updated 3 years ago
- 4096bit RSA project, with verilog code, python test code, etc☆45Updated 5 years ago
- An open source FPGA miner for Blakecoin☆52Updated 10 years ago
- Bitcoin miner for Xilinx FPGAs☆97Updated 12 years ago
- Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.☆134Updated 2 years ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆31Updated 6 years ago
- Zcash FPGA acceleration engine☆127Updated 4 years ago
- Simple hash table on Verilog (SystemVerilog)☆50Updated 9 years ago
- ☆81Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- SpinalHDL - Cryptography libraries☆57Updated last year
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆65Updated 2 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆40Updated 8 years ago
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Updated 4 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆33Updated last year
- FPGA referrence implementation for aion equihash 2109☆15Updated 7 years ago
- Implementation of RSA algorithm on FPGA using Verilog☆28Updated 7 years ago
- SHA-256 IP core for ZedBoard (Zynq SoC)☆30Updated 7 years ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆37Updated 4 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 6 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆120Updated last month
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆24Updated 9 months ago