stremovsky / moneroasicLinks
Cryptonight Monero Verilog code for ASIC
☆20Updated 7 years ago
Alternatives and similar repositories for moneroasic
Users that are interested in moneroasic are comparing it to the libraries listed below
Sorting:
- SHA256 in (System-) Verilog / Open Source FPGA Miner☆79Updated 7 years ago
- Verilog implementation of the SHA-512 hash function.☆39Updated 3 months ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆31Updated 6 years ago
- Hardware implementation of the SHA-256 cryptographic hash function☆345Updated 3 weeks ago
- 4096bit RSA project, with verilog code, python test code, etc☆44Updated 5 years ago
- FIPS 202 compliant SHA-3 core in Verilog☆22Updated 4 years ago
- Simple hash table on Verilog (SystemVerilog)☆49Updated 9 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆38Updated last year
- Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field☆23Updated 8 years ago
- Zcash FPGA acceleration engine☆125Updated 4 years ago
- ☆81Updated last year
- SQRL FK33 board files, example designs and scripts.☆17Updated 2 years ago
- Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.☆134Updated 2 years ago
- SpinalHDL - Cryptography libraries☆56Updated 11 months ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆39Updated 8 years ago
- FPGA implementation of a physical unclonable function for authentication☆33Updated 8 years ago
- Implementation of RSA algorithm on FPGA using Verilog☆28Updated 6 years ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆24Updated 8 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- SHA-256 IP core for ZedBoard (Zynq SoC)☆30Updated 7 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆65Updated 2 years ago
- A list of VHDL codes implementing cryptographic algorithms☆27Updated 3 years ago
- Verilog implementation of the SHA-1 cryptgraphic hash function☆52Updated 3 months ago
- Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (main project repo). Taped out in December…☆22Updated 4 years ago
- XCrypto: a cryptographic ISE for RISC-V☆93Updated 2 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆39Updated 5 years ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆41Updated 2 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Tutorials on HLS Design☆52Updated 5 years ago
- True Random Number Generator core implemented in Verilog.☆75Updated 4 years ago