Alternatives and similar repositories for moneroasic:

Users that are interested in moneroasic are comparing it to the libraries listed below

• unixb0y / SystemVerilogSHA256
  SHA256 in (System-) Verilog / Open Source FPGA Miner
  ☆78Updated 7 years ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆36Updated last year
• d953i / SQRL_FK33
  SQRL FK33 board files, example designs and scripts.
  ☆17Updated 2 years ago
• ZcashFoundation / zcash-fpga
  Zcash FPGA acceleration engine
  ☆123Updated 4 years ago
• kramble / FPGA-Blakecoin-Miner
  An open source FPGA miner for Blakecoin
  ☆51Updated 10 years ago
• secworks / sha512
  Verilog implementation of the SHA-512 hash function.
  ☆38Updated 3 weeks ago
• teknohog / Xilinx-Serial-Miner
  Bitcoin miner for Xilinx FPGAs
  ☆97Updated 11 years ago
• fatestudio / RSA4096
  4096bit RSA project, with verilog code, python test code, etc
  ☆45Updated 5 years ago
• ljhsiun2 / EllipticCurves_SystemVerilog
  Elgamal's over Elliptic Curves
  ☆19Updated 6 years ago
• Goshik92 / SHA256Hasher
  SHA-256 IP core for ZedBoard (Zynq SoC)
  ☆31Updated 6 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆48Updated 3 years ago
• pedrorivera / SiaFpgaMiner
  VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin
  ☆62Updated 7 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• johan92 / fpga-hash-table
  Simple hash table on Verilog (SystemVerilog)
  ☆48Updated 9 years ago
• aionnetwork / aion_epic_fpgaminer
  FPGA referrence implementation for aion equihash 2109
  ☆14Updated 6 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆44Updated 2 years ago
• raya4213 / VerilogCodeECC
  Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field
  ☆22Updated 8 years ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆29Updated 4 years ago
• altASIC / Open-CryptoNight-ASIC
  Open source hardware implementation of classic CryptoNight
  ☆37Updated 2 years ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆38Updated 5 years ago
• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆36Updated 4 years ago
• oprecomp / DDR4_controller
  ☆55Updated 4 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 4 years ago
• fatestudio / RSA4096_NEW
  ☆13Updated 10 years ago
• 0x2fed / FPGA-GroestlCoin-Miner
  An Open Source FPGA GroestlCoin Miner
  ☆10Updated 7 years ago
• pulp-platform / axi_spi_slave
  ☆25Updated 3 years ago
• supranational / vdf-fpga
  Implementation of an RSA VDF evaluator targeting FPGAs.
  ☆48Updated 5 years ago
• kgpai94 / ECC-Encryption-System
  This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…
  ☆31Updated 6 years ago
• fpgaminer / Open-Source-FPGA-Bitcoin-Miner
  A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open d…
  ☆172Updated 3 years ago
• mih0 / FPGA_Mining_AWS
  Example verilog / miner for crypto mining using AWS F1 instances
  ☆30Updated 6 years ago