A 64-stage pipelined MD5 implementation written in verliog. Runs reliably on a DE0-Nano at 100mhz, computing 100 million hashes per second.
☆68Feb 15, 2022Updated 4 years ago
Alternatives and similar repositories for fpga-md5-cracker
Users that are interested in fpga-md5-cracker are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Hardware MD5 Cracker for the Cyclone V SoC☆12Mar 25, 2015Updated 11 years ago
- MD5 core in verilog☆13May 1, 2012Updated 14 years ago
- DES cracking machine on FPGA☆19Jul 7, 2019Updated 7 years ago
- FPGA based modular synth.☆20Jan 8, 2017Updated 9 years ago
- Hardware implementation of HDR image producing algorithm☆16Sep 30, 2022Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆16Nov 8, 2025Updated 9 months ago
- We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.☆32May 18, 2019Updated 7 years ago
- HurmaDB is a key-value storage with REST interface based on RocksDB☆17Dec 8, 2022Updated 3 years ago
- ☆15Aug 1, 2023Updated 3 years ago
- WPA-PSK cracking for FPGA devices☆19May 3, 2017Updated 9 years ago
- Matrix multiplication on multiple Nios II cores☆17Feb 12, 2020Updated 6 years ago
- descrypt-ztex-bruteforcer☆16Jul 24, 2014Updated 12 years ago
- SPI-Flash XIP Interface (Verilog)☆52Oct 24, 2021Updated 4 years ago
- Metasploit Framework☆11Sep 5, 2017Updated 8 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- AES加密解密算法的Verilog实现☆71Jan 17, 2016Updated 10 years ago
- Munk - Visualize Splunk Architecture in Maltego☆13Sep 19, 2014Updated 11 years ago
- Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs☆49Aug 31, 2017Updated 9 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆21Feb 12, 2018Updated 8 years ago
- USB-OTG Keyboard on STM32F4-Discovery☆33May 31, 2014Updated 12 years ago
- A repository of IPs for hardware computer vision (FPGA)☆97Oct 21, 2015Updated 10 years ago
- Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determine…☆15Jun 15, 2016Updated 10 years ago
- Airprobe with a simple GPRS support. Single-ARFCN downlink and uplink supported. No frequency-hopping supported. No Timing Advance for up…☆20Oct 15, 2011Updated 14 years ago
- EtherPIPE: an Ethernet character device for packet processing☆17Dec 27, 2014Updated 11 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- FPGA controller for SSD1306 OLED module on SPI. Optimised for GOWIN FPGA☆17Oct 11, 2018Updated 7 years ago
- FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.☆15Jul 19, 2012Updated 14 years ago
- RetroCade Synth - C64 SID, YM2149, and POKEY audio chips with MIDI interface.☆40Jan 5, 2017Updated 9 years ago
- IP operations in verilog (simulation and implementation on ice40)☆65Oct 24, 2019Updated 6 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 10 years ago
- Verilog Ethernet Switch (layer 2)☆59Oct 18, 2023Updated 2 years ago
- Identifies ASL Hand Gesture for numbers using image processing in verilog☆15May 3, 2012Updated 14 years ago
- Using the Quartus II software, a OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the d…☆15Dec 29, 2016Updated 9 years ago
- ☆11May 24, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- cryptography ip-cores in vhdl / verilog☆42Feb 20, 2021Updated 5 years ago
- 关于CIC滤波器、ISOP补偿器、HB滤波器的相关Matlab仿真与FPGA工程☆17Dec 25, 2023Updated 2 years ago
- Using the Quartus II software, an OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the …☆19Dec 29, 2016Updated 9 years ago
- ydlidar sdk(new version)☆16Nov 26, 2018Updated 7 years ago
- PLEASE MOVE TO PAWSv2☆16Feb 2, 2022Updated 4 years ago
- Xilinx AR65444 - Xilinx PCIe DMA Driver for linux☆22May 10, 2019Updated 7 years ago
- SOC system using verilog on FPGA devices.☆10Jan 11, 2016Updated 10 years ago