Alternatives and similar repositories for ZynqBTC

Users that are interested in ZynqBTC are comparing it to the libraries listed below

• bmartini / zynq-axis
  Hardware, Linux Driver and Library for the Zynq AXI DMA interface
  ☆101Updated 6 years ago
• teknohog / Xilinx-Serial-Miner
  Bitcoin miner for Xilinx FPGAs
  ☆97Updated 12 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆101Updated 6 years ago
• ATaylorCEngFIET / MicroZed-Chronicles
  Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog
  ☆194Updated 6 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆96Updated 3 years ago
• fpgaminer / Open-Source-FPGA-Bitcoin-Miner
  A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open d…
  ☆173Updated 3 years ago
• fpgadeveloper / zedboard-axi-dma
  Demonstration of the AXI DMA engine on the ZedBoard
  ☆53Updated 4 years ago
• Digilent / ZYBO
  ☆63Updated 8 years ago
• analogdevicesinc / fpgahdl_xilinx
  (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…
  ☆89Updated 6 years ago
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆73Updated 6 years ago
• imrickysu / ZYNQ-Cookbook
  This is a wiki and code sharing for ZYNQ
  ☆73Updated 9 years ago
• fpgadeveloper / microzed-axi-dma
  Demonstration of the AXI DMA engine on the MicroZed
  ☆26Updated 4 years ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆66Updated last month
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆124Updated 5 years ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆99Updated 6 years ago
• kramble / FPGA-Litecoin-Miner
  A litecoin scrypt miner implemented with FPGA on-chip memory.
  ☆288Updated 10 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 7 years ago
• Xilinx / SDSoC_Examples
  ☆84Updated 4 years ago
• DigilentInc / vivado-library
  ☆35Updated 7 years ago
• h-nasiri / Zynq-Linux-DMA
  DMA enabled Zynq PS-PL communication to implement high throughput data transfer between Linux applications and user IP core.
  ☆39Updated 8 years ago
• fpgadeveloper / ethernet-fmc-zynq-gem
  Example design for the Ethernet FMC using the hard GEMs of the Zynq
  ☆56Updated last month
• malkadi / FGPU
  FGPU is a soft GPU architecture general purpose computing
  ☆57Updated 4 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆34Updated 7 years ago
• Avnet / bdf
  Avnet Board Definition Files
  ☆134Updated 2 months ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆38Updated last year
• forconesi / nfmac10g
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆64Updated 8 years ago
• xupgit / FPGA-Design-Flow-using-Vivado
  This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
  ☆102Updated 5 years ago
• gtaylormb / ultra96v2_imx219_to_displayport
  Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL
  ☆70Updated 3 years ago
• StefanSredojevic / Deep-Neural-Network-Hardware-Accelerator
  SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…
  ☆110Updated 5 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago