stiggy87 / ZynqBTCLinks
A Bitcoin miner for the Zynq chip utilizing the Zedboard.
☆107Updated 2 years ago
Alternatives and similar repositories for ZynqBTC
Users that are interested in ZynqBTC are comparing it to the libraries listed below
Sorting:
- Bitcoin miner for Xilinx FPGAs☆99Updated 12 years ago
- A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open d…☆176Updated 3 years ago
- Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog☆200Updated 7 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆105Updated 7 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- Hardware, Linux Driver and Library for the Zynq AXI DMA interface☆104Updated 7 years ago
- Python tools for Vivado Projects☆72Updated 6 years ago
- ☆65Updated 8 years ago
- ☆113Updated 9 months ago
- (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…☆89Updated 7 years ago
- Demonstration of the AXI DMA engine on the MicroZed☆26Updated 4 years ago
- This is a wiki and code sharing for ZYNQ☆74Updated 9 years ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆97Updated 3 years ago
- Avnet Board Definition Files☆139Updated 3 months ago
- Demonstration of the AXI DMA engine on the ZedBoard☆55Updated 4 years ago
- DMA enabled Zynq PS-PL communication to implement high throughput data transfer between Linux applications and user IP core.☆41Updated 8 years ago
- ☆70Updated 5 months ago
- A litecoin scrypt miner implemented with FPGA on-chip memory.☆291Updated 11 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow☆90Updated 10 months ago
- Example design for the Ethernet FMC using the hard GEMs of the Zynq☆61Updated 7 months ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 5 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆39Updated last year
- FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq-Zybo:PYNQ-Z1 Altera:de0-nano-soc:de1…☆168Updated last month
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆72Updated 7 months ago
- Example designs for FPGA Drive FMC☆284Updated last year
- SHA256 in (System-) Verilog / Open Source FPGA Miner☆83Updated 7 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- ☆63Updated 7 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆70Updated 8 years ago