A Bitcoin miner for the Zynq chip utilizing the Zedboard.
☆107Aug 10, 2023Updated 2 years ago
Alternatives and similar repositories for ZynqBTC
Users that are interested in ZynqBTC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An Open Source FPGA GroestlCoin Miner☆10Feb 11, 2018Updated 8 years ago
- A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open d…☆1,374May 16, 2022Updated 4 years ago
- A litecoin scrypt miner implemented with FPGA on-chip memory.☆291Sep 22, 2014Updated 11 years ago
- ☆19May 1, 2018Updated 8 years ago
- SHA-256 IP core for ZedBoard (Zynq SoC)☆31Jun 22, 2018Updated 8 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A less cramped XMOS xCORE200 Platform based DSP and microcontroller PCB design - open source hardware☆15Apr 4, 2019Updated 7 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆109Nov 14, 2018Updated 7 years ago
- Linux Driver for the Zynq FPGA DMA engine☆90Feb 12, 2015Updated 11 years ago
- Fork of Xilinx's Linux repo that adds support for Digilent boards☆10Feb 14, 2018Updated 8 years ago
- ☆57May 9, 2023Updated 3 years ago
- Official Linux kernel for Parallella☆42Oct 10, 2013Updated 12 years ago
- Open Source ZYNQ Board☆31Aug 19, 2015Updated 10 years ago
- QCD for Intel Xeon Phi and Xeon processors☆14Mar 20, 2024Updated 2 years ago
- ☆10Sep 7, 2023Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A simplified version of an FPGA bitcoin miner☆53Jul 9, 2019Updated 7 years ago
- Digital circuit simulator, written by Jeffery P. Hansen☆11Aug 29, 2019Updated 6 years ago
- imx bootrom plugin☆13Oct 9, 2018Updated 7 years ago
- Wishbone <-> AXI converters☆13Jun 1, 2015Updated 11 years ago
- RISC-V Rocket on the Digilent Zybo Board☆21Aug 6, 2014Updated 11 years ago
- Docker image with Xilinx FPGA Tools (Vivado - SDAccel) usable with GUI on Mac☆10Oct 6, 2018Updated 7 years ago
- This is a wiki and code sharing for ZYNQ☆74Apr 2, 2016Updated 10 years ago
- Share JTAG chain within RISCV core and Xilinx FPGA.☆10Sep 17, 2019Updated 6 years ago
- Hardware, Linux Driver and Library for the Zynq AXI DMA interface☆105Jul 21, 2018Updated 8 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- ☆27Jul 6, 2018Updated 8 years ago
- Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog☆202Oct 9, 2018Updated 7 years ago
- Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.☆17Jan 10, 2018Updated 8 years ago
- PetaLinux BSPs for Digilent☆16Aug 15, 2016Updated 9 years ago
- JTAG communication using the FTDI FT232R chip.☆23Mar 7, 2012Updated 14 years ago
- Identifies ASL Hand Gesture for numbers using image processing in verilog☆15May 3, 2012Updated 14 years ago
- Code that goes with the Digilent Maker Space projects- to share and improve all code here is shared under the Creative Commons 3.0 Licens…☆21Jun 5, 2014Updated 12 years ago
- Display ov7670 camera video on VGA monitors through Video DMA on ZedBoard☆19Jun 20, 2017Updated 9 years ago
- WaRP7 User Guide Source. For binary releases go to the release tab☆12Apr 8, 2018Updated 8 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"☆776May 26, 2017Updated 9 years ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆20Nov 23, 2023Updated 2 years ago
- A place to store the code for FPGA tutorial projects I have written for the Parallella [http://parallellagram.org]☆11Oct 19, 2014Updated 11 years ago
- riscv uclinux☆15Aug 9, 2019Updated 6 years ago
- FPGA-based shield for Arduino☆73Jun 30, 2015Updated 11 years ago
- VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin☆63Feb 7, 2018Updated 8 years ago