kramble / DE0-Nano-BitCoin-Miner
DE0 Nano port of fpgaminer - this is based on https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner
☆90Updated 10 years ago
Related projects ⓘ
Alternatives and complementary repositories for DE0-Nano-BitCoin-Miner
- An open source FPGA miner for Blakecoin☆50Updated 10 years ago
- DUAL Spartan6 Development Platform☆86Updated 6 years ago
- A litecoin scrypt miner implemented with FPGA on-chip memory.☆280Updated 10 years ago
- Bitcoin miner for Xilinx FPGAs☆93Updated 11 years ago
- A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open d…☆171Updated 2 years ago
- A completely open source implementation of a Bitcoin Miner for Altera FPGAs. This project hopes to promote the free and open development …☆50Updated 11 years ago
- Open Source Bitcoin Vanity Address Generation on FPGAs☆27Updated 2 years ago
- SHA256 in (System-) Verilog / Open Source FPGA Miner☆75Updated 6 years ago
- Open source hardware implementation of classic CryptoNight☆35Updated last year
- A Bitcoin miner for the Zynq chip utilizing the Zedboard.☆100Updated last year
- A simplified version of an FPGA bitcoin miner☆48Updated 5 years ago
- VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin☆62Updated 6 years ago
- FPGA core for SHA256d mining targeting Lattice iCE40 devices.☆20Updated 3 years ago
- A simple SHA-256 implementation in VHDL☆22Updated 6 years ago
- FPGA development platform for high-performance RF and digital design☆30Updated 8 years ago
- ☆65Updated 9 years ago
- The CAT Board is a Raspberry Pi HAT with a Lattice iCE40HX FPGA.☆60Updated 8 months ago
- Cryptonight Monero Verilog code for ASIC☆20Updated 6 years ago
- EBAZ4205 is Xilinx Zynq based mining board used in Ebang Ebit E9+ bitcoin miner machine.☆62Updated 8 months ago
- ☆64Updated 10 years ago
- Schematics and sample projects for S9 antminer control board sold as development board☆76Updated 3 years ago
- FPGA-based shield for Arduino☆72Updated 9 years ago
- ZPUino HDL implementation☆88Updated 6 years ago
- PanoLogic Zero Client G1 reverse engineering info☆69Updated 7 months ago
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆27Updated 2 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆37Updated 8 years ago
- ☆51Updated 2 years ago
- artix-7 PCIe dev board☆24Updated 7 years ago
- Collection of open-source peripherals in Verilog☆173Updated 2 years ago