martinafogliato / Sha256_Hw_AcceleratorLinks
SHA256 hardware accelerator, synthesized for and mapped on the Zynq core of the Zybo board by Digilent
☆27Updated 7 years ago
Alternatives and similar repositories for Sha256_Hw_Accelerator
Users that are interested in Sha256_Hw_Accelerator are comparing it to the libraries listed below
Sorting:
- A simple DDR3 memory controller☆61Updated 2 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆43Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- UART -> AXI Bridge☆67Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- ☆28Updated 4 years ago
- Open source FPGA-based NIC and platform for in-network compute☆67Updated 3 months ago
- Ethernet 10GE MAC☆46Updated 11 years ago
- I2C controller core☆47Updated 2 years ago
- Ethernet interface modules for Cocotb☆71Updated 3 months ago
- An implementation of the CORDIC algorithm in Verilog.☆105Updated 7 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆92Updated 3 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆46Updated 11 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆42Updated 2 months ago
- UART models for cocotb☆32Updated 3 months ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆71Updated 7 months ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆76Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆52Updated 2 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆46Updated 9 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated 2 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- Verilog wishbone components☆124Updated last year
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- Verilog Content Addressable Memory Module☆113Updated 3 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- ☆43Updated 3 years ago
- Altera Advanced Synthesis Cookbook 11.0☆111Updated 2 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 5 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago