secworks / blake2sLinks
Verilog implementation of the 32-bit version of the Blake2 hash function
☆21Updated 5 months ago
Alternatives and similar repositories for blake2s
Users that are interested in blake2s are comparing it to the libraries listed below
Sorting:
- IP submodules, formatted for easier CI integration☆30Updated 2 months ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated 2 months ago
- FPGA board-level debugging and reverse-engineering tool☆38Updated 2 years ago
- Small footprint and configurable SPI core☆43Updated this week
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Virtual Development Board☆61Updated 3 years ago
- PCIe analyzer experiments☆61Updated 5 years ago
- Exploring gate level simulation☆58Updated 4 months ago
- A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.☆30Updated 5 years ago
- Experiments with Yosys cxxrtl backend☆49Updated 8 months ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 3 years ago
- ☆23Updated 3 years ago
- Open Source AES☆31Updated last year
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- SymbiFlow WIP changes for Yosys Open SYnthesis Suite☆39Updated last year
- Test of the USB3 IP Core from Daisho on a Xilinx device☆99Updated 5 years ago
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆91Updated 10 months ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 3 years ago
- Verilog Language Extension for Visual Studio☆19Updated 4 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆67Updated last week
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Generic Logic Interfacing Project☆47Updated 5 years ago
- Utilities for working with a Wishbone bus in an embedded device☆45Updated 3 weeks ago
- Project X-Ray Database: XC7 Series☆70Updated 3 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 3 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆18Updated 2 years ago
- Basic loadout for SQRL Acorn CLE 215/215+ board. Blinks all LEDs, outputs square waves on all 12 GPIO outputs☆69Updated 3 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆54Updated 3 months ago
- Repository and Wiki for Chip Hack events.☆51Updated 4 years ago