secworks / blake2s

Related projects ⓘ

Alternatives and complementary repositories for blake2s

• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆36Updated 3 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆54Updated last month
• sparrowgrine / prjtritium
  ☆22Updated 2 years ago
• betrusted-io / gateware
  IP submodules, formatted for easier CI integration
  ☆28Updated last year
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆20Updated 3 years ago
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated 7 months ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆36Updated 10 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆39Updated 3 weeks ago
• grayresearch / s4ga
  a small simple slow serial FPGA core
  ☆16Updated 3 years ago
• mattvenn / understanding-tinyfpga-bootloader
  understanding the tinyfpga bootloader
  ☆24Updated 6 years ago
• defparam / PCI2Nano-PCB
  An FPGA/PCI Device Reference Platform
  ☆28Updated 3 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• hamsternz / MMCM_GPSDO
  An all-digital GPS disciplined oscillator using MMCM phase shift.
  ☆27Updated 2 years ago
• ZiyangYE / General-Slow-DDR3-Interface
  A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
  ☆36Updated 6 months ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆47Updated this week
• GuzTech / shdl6800
  shdl6800: A 6800 processor written in SpinalHDL
  ☆26Updated 4 years ago
• mattvenn / xor_vga_fpga
  playing with XOR video patterns on an FPGA
  ☆13Updated 3 years ago
• j-marjanovic / otma-pin-re
  ☆15Updated 3 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆36Updated 6 years ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 3 years ago
• brouhaha / xchange
  Change part number or package in a Xilinx 7-series FPGA bitstream
  ☆36Updated 4 years ago
• tomverbeure / ecp5_jtag
  Use ECP5 JTAG port to interact with user design
  ☆24Updated 3 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆60Updated 3 weeks ago
• paulscherrerinstitute / xvcSupport
  ☆17Updated 4 years ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆36Updated last year
• kazkojima / colorlight-i5-tips
  Tiny tips for Colorlight i5 FPGA board
  ☆55Updated 3 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆36Updated last year