Alternatives and similar repositories for rvkrypto-fips:

Users that are interested in rvkrypto-fips are comparing it to the libraries listed below

• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆34Updated 4 years ago
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆37Updated 3 months ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆29Updated 2 months ago
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆43Updated last week
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆36Updated last year
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆19Updated last month
• scarv / xcrypto
  XCrypto: a cryptographic ISE for RISC-V
  ☆92Updated 2 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated 2 years ago
• emb-riscv / specs-markdown
  The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.
  ☆27Updated 3 years ago
• rdolbeau / VexRiscvBPluginGenerator
  ☆17Updated 2 years ago
• RISCV-on-Microsemi-FPGA / FreeRTOS
  FreeRTOS for RISC-V
  ☆26Updated 6 years ago
• hex-five / multizone-sdk
  MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn'…
  ☆83Updated last year
• comparch-security / chipyard-random-llc
  A Rocket-Chip with a Dynamically Randomized LLC
  ☆12Updated 4 months ago
• riscv / virtual-memory
  ☆36Updated 3 years ago
• uec-hanken / tee-hardware
  TEE hardware - based on the chipyard repository - hardware to accelerate TEE
  ☆20Updated 2 years ago
• riscvarchive / riscv-tee
  ☆38Updated 2 years ago
• ucb-bar / libgloss-htif
  A libgloss replacement for RISC-V that supports HTIF
  ☆28Updated 9 months ago
• tenstorrent / rv-core-dv-kit
  ☆24Updated 2 years ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆31Updated last week
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆83Updated this week
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆84Updated this week
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆35Updated 3 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆57Updated last week
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆21Updated 4 months ago
• riscv-admin / iopmp
  Group administration repository for Tech: IOPMP Task Group
  ☆13Updated last month
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆30Updated 9 months ago
• riscv / riscv-CMOs
  ☆83Updated 2 years ago
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 3 years ago
• Ko- / riscvcrypto
  Optimized assembly implementations of crypto for the RV32I (RISC-V) architecture
  ☆31Updated 4 years ago