Alternatives and similar repositories for rvkrypto-fips:

Users that are interested in rvkrypto-fips are comparing it to the libraries listed below

• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆35Updated 4 years ago
• scarv / xcrypto
  XCrypto: a cryptographic ISE for RISC-V
  ☆92Updated 2 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆29Updated 3 months ago
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆37Updated 4 months ago
• AsmOptC-RiscV / Assembly-Optimized-C-RiscV
  ☆15Updated 4 years ago
• keystone-enclave / sm
  Keystone security monitor library for opensbi (Discountinued after monorepo-izing)
  ☆13Updated 2 years ago
• keystone-enclave / riscv-pk
  Security monitor for Keystone Enclave (mirror of riscv-pk). Will be deprecated when openSBI port is ready
  ☆35Updated 3 years ago
• Ko- / riscvcrypto
  Optimized assembly implementations of crypto for the RV32I (RISC-V) architecture
  ☆31Updated 4 years ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆36Updated last year
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆19Updated 3 weeks ago
• riscvarchive / riscv-tee
  ☆38Updated 2 years ago
• fintelia / riscv-decode
  Simple library for decoding RISC-V instructions
  ☆22Updated 6 months ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆58Updated this week
• uec-hanken / tee-hardware
  TEE hardware - based on the chipyard repository - hardware to accelerate TEE
  ☆21Updated 2 years ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆35Updated last month
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆44Updated 2 weeks ago
• riscv-non-isa / riscv-ap-tee
  This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the …
  ☆52Updated this week
• hex-five / multizone-sdk
  MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn'…
  ☆83Updated last year
• riscv / virtual-memory
  ☆36Updated 3 years ago
• rdolbeau / VexRiscvBPluginGenerator
  ☆17Updated 2 years ago
• riscv / riscv-test-env
  ☆45Updated 2 months ago
• CTSRD-CHERI / garnet
  Amazon F1-inspired Xilinx VCU118 hardware design framework
  ☆12Updated 4 years ago
• GMUCERG / LWC
  Development Package for the Hardware API for Lightweight Cryptography
  ☆15Updated last year
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆30Updated 10 months ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆35Updated this week
• riscv-admin / iopmp
  Group administration repository for Tech: IOPMP Task Group
  ☆13Updated 2 months ago
• emb-riscv / specs-markdown
  The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.
  ☆27Updated 3 years ago
• riscv / riscv-CMOs
  ☆85Updated 2 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated 2 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆87Updated this week