Alternatives and similar repositories for cheribuild

Users that are interested in cheribuild are comparing it to the libraries listed below

• CTSRD-CHERI / qemu
  QEMU with support for CHERI
  ☆58Updated last month
• CTSRD-CHERI / llvm-project
  Fork of LLVM adding CHERI support
  ☆52Updated this week
• CTSRD-CHERI / cheribsd
  FreeBSD adapted for CHERI-RISC-V and Arm Morello.
  ☆179Updated this week
• CTSRD-CHERI / cheri-exercises
  Learning exercises for CHERI
  ☆21Updated 7 months ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆59Updated last month
• CTSRD-CHERI / cherios
  CheriOS -- a minimal microkernel that demonstrates "clean-slate" CHERI memory protection and object capabilities
  ☆40Updated 2 years ago
• CTSRD-CHERI / cheri-c-programming
  CHERI C/C++ Programming Guide
  ☆31Updated last month
• ARM-software / asl-interpreter
  Example implementation of Arm's Architecture Specification Language (ASL)
  ☆117Updated 5 years ago
• rems-project / sail-arm
  Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model
  ☆80Updated this week
• comsec-group / cascade-artifacts
  Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)
  ☆129Updated 9 months ago
• riscv-non-isa / riscv-security-model
  RISC-V Security Model
  ☆30Updated 3 weeks ago
• CTSRD-CHERI / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆32Updated this week
• CTSRD-CHERI / cheri-specification
  CHERI ISA Specification
  ☆24Updated 10 months ago
• CHERIoT-Platform / cheriot-sail
  Sail code model of the CHERIoT ISA
  ☆38Updated last week
• riscv / riscv-cfi
  This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …
  ☆87Updated 3 weeks ago
• rems-project / isla
  Symbolic execution tool for Sail ISA specifications
  ☆67Updated last week
• alastairreid / asl-interpreter
  Example implementation of Arm's Architecture Specification Language (ASL)
  ☆40Updated 3 weeks ago
• au-ts / lionsos
  A secure, fast, and adaptable OS based on the seL4 microkernel
  ☆136Updated this week
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆68Updated last week
• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆186Updated 3 weeks ago
• isec-tugraz / transientfail
  Website and PoC collection for transient execution attacks
  ☆182Updated last year
• rems-project / rmem
  rmem public repo
  ☆42Updated last week
• seL4 / microkit
  Microkit - A simple operating system framework for the seL4 microkernel
  ☆119Updated this week
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆151Updated last week
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆105Updated 2 months ago
• rivosinc / salus
  Risc-V hypervisor for TEE development
  ☆116Updated 2 weeks ago
• seL4 / seL4_libs
  No-assurance libraries for rapid-prototyping of seL4 apps.
  ☆54Updated 2 months ago
• pydrofoil / pydrofoil
  A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one
  ☆73Updated this week
• ibm-research / speculator
  Tool to Analyze Speculative Execution Attacks and Mitigations
  ☆55Updated 3 years ago
• tudinfse / SpecFuzz
  A tool to enable fuzzing for Spectre vulnerabilities
  ☆30Updated 5 years ago