qmn / deweyLinks
C version of PERSHING, a place-and-route tool for Minecraft Redstone circuits
☆22Updated 7 years ago
Alternatives and similar repositories for dewey
Users that are interested in dewey are comparing it to the libraries listed below
Sorting:
- An automatic place-and-route tool for Minecraft redstone circuits☆25Updated 9 years ago
- Verilog implementation of pipelined cpu☆12Updated 4 years ago
- Verik toolchain☆44Updated 2 years ago
- Hardware generator debugger☆74Updated last year
- Verilog implementation of various types of CPUs☆60Updated 5 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 2 months ago
- A SystemVerilog source file pickler.☆59Updated 9 months ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆34Updated last month
- ASIC implementation flow infrastructure☆47Updated last week
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆225Updated last year
- ACT hardware description language and core tools.☆114Updated this week
- An introductory guide to Bluespec (BSV)☆62Updated 6 years ago
- An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.☆14Updated 6 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- Open-source RTL logic simulator with CUDA acceleration☆188Updated last month
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆227Updated this week
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- 21st century electronic design automation tools, written in Rust.☆31Updated last week
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 4 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆144Updated last month
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆284Updated 2 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆158Updated 5 years ago
- Marginally better than redstone☆99Updated 4 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆106Updated 2 months ago
- Various examples for Chisel HDL☆30Updated 3 years ago