Alternatives and similar repositories for dewey

Users that are interested in dewey are comparing it to the libraries listed below

• qmn / pershing
  An automatic place-and-route tool for Minecraft redstone circuits
  ☆25Updated 9 years ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆327Updated 3 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 3 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆290Updated 3 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆264Updated last week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆59Updated 10 months ago
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆216Updated last week
• PeterAaser / RISCV-FiveStage
  Marginally better than redstone
  ☆99Updated 5 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆161Updated 5 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆145Updated 3 weeks ago
• ucb-bar / berkeley-hardfloat
  ☆338Updated 11 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆209Updated 5 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• AntonLydike / riscemu
  RISC-V emulator in python
  ☆60Updated last year
• kcamenzind / BluespecIntroGuide
  An introductory guide to Bluespec (BSV)
  ☆64Updated 6 years ago
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆213Updated this week
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆121Updated 2 years ago
• wallento / riscv-python-model
  Python Model of the RISC-V ISA
  ☆54Updated 3 years ago
• frwang96 / verik
  Verik toolchain
  ☆44Updated 2 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆75Updated last year
• ejrh / cpu
  A very primitive but hopefully self-educational CPU in Verilog
  ☆148Updated 10 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 5 months ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆140Updated 11 months ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆124Updated last year
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆155Updated 3 months ago
• seunghyukcho / pipelined-cpu-verilog
  Verilog implementation of pipelined cpu
  ☆12Updated 4 years ago
• classabbyamp / espresso-logic
  A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.
  ☆154Updated 5 years ago
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆119Updated 2 weeks ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆31Updated 10 years ago
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆208Updated last year