Alternatives and similar repositories for dewey

Users that are interested in dewey are comparing it to the libraries listed below

• qmn / pershing
  An automatic place-and-route tool for Minecraft redstone circuits
  ☆25Updated 9 years ago
• Raptor324 / HBM-Modernized
  HBM Modernized - 1.20.1 port of well-known HBM's NTM
  ☆29Updated this week
• Kenny2github / V2MC
  Synthesize Verilog to Minecraft redstone
  ☆21Updated last year
• seunghyukcho / pipelined-cpu-verilog
  Verilog implementation of pipelined cpu
  ☆12Updated 4 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆183Updated 8 months ago
• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• wallento / riscv-python-model
  Python Model of the RISC-V ISA
  ☆62Updated 3 years ago
• kcamenzind / BluespecIntroGuide
  An introductory guide to Bluespec (BSV)
  ☆66Updated 6 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆153Updated 3 weeks ago
• frwang96 / verik
  Verik toolchain
  ☆45Updated 3 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆225Updated 10 months ago
• PeterAaser / RISCV-FiveStage
  Marginally better than redstone
  ☆102Updated 5 years ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆308Updated 3 months ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆331Updated 4 years ago
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆36Updated 5 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆170Updated 5 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• j-marjanovic / chisel-stuff
  Various examples for Chisel HDL
  ☆30Updated 3 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆23Updated last week
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆145Updated last year
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆153Updated 2 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆110Updated 5 months ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆55Updated 2 weeks ago
• BSVLang / Main
  Main page
  ☆129Updated 5 years ago
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆122Updated this week
• IBM / perfect-chisel
  Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program
  ☆30Updated 4 months ago
• classabbyamp / espresso-logic
  A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.
  ☆168Updated 5 years ago