Core protocol to AXI bridge
☆11Sep 30, 2019Updated 7 years ago
Alternatives and similar repositories for core2axi
Users that are interested in core2axi are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Implementation of a circular queue in hardware using verilog.☆18Mar 22, 2019Updated 7 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆28Jul 27, 2026Updated 3 months ago
- ☆11Dec 9, 2023Updated 2 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- RISC-V soft-core PEs for TaPaSCo☆24Jul 24, 2026Updated 3 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Collection of IPs based on AMBA (AHB, APB, AXI) protocols☆19Feb 1, 2017Updated 9 years ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆26Sep 10, 2026Updated last month
- the xoroshiro32++ and xoroshiro64++ PRNG algorthims by David Blackman and Sebastiano Vigna in C++, Verilog, VHDL and SpinalHDL.☆16Dec 2, 2018Updated 7 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Nov 27, 2018Updated 7 years ago
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Oct 19, 2020Updated 6 years ago
- APB Timer Unit☆14Oct 30, 2025Updated last year
- BP list decoding for polar codes☆14Sep 1, 2023Updated 3 years ago
- ☆16Mar 17, 2026Updated 7 months ago
- APB4 Multiplexor☆15May 10, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- GSI Timing Gateware and Tools☆14Updated this week
- Notes from learning RISC-V☆12Jun 30, 2026Updated 4 months ago
- ☆21Dec 9, 2018Updated 7 years ago
- An FPGA-accelerated platform for FEC analysis of wireline systems☆14Jan 21, 2025Updated last year
- Simple UART transmitter and receiver☆35Jun 11, 2019Updated 7 years ago
- A light-weight hardware oriented synchronous stream cipher.☆12Mar 19, 2022Updated 4 years ago
- This project is made to generate Polar decoders (unrolled decoders).☆15May 31, 2025Updated last year
- A fork of TinyMLPerf modified to use our of TensorFlow Lite for Microcontrollers utilises a part of the RISC-V Vector Extension to improv…☆11Jan 18, 2021Updated 5 years ago
- SGen is a generator capable of producing efficient hardware designs operating on streaming datasets. “Streaming” means that the dataset i…☆28Nov 11, 2025Updated 11 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆22Feb 4, 2025Updated last year
- RMII Firewall FPGA☆25Dec 2, 2019Updated 6 years ago
- ☆15Jul 5, 2019Updated 7 years ago
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆17Apr 12, 2020Updated 6 years ago
- A min-sum LDPC decoder written in SystemVerilog (IEEE 1800-2012)☆12Jan 8, 2021Updated 5 years ago
- ECE385 Final Project - Raiden Shooter Game - at ZJU-UIUC Institute; w/ 16-bit VGA, Sound and Ethernet☆15Dec 4, 2020Updated 5 years ago
- Easy to use framework for ROS2 FPGA-based hardware acceleration; Supports Pub/Sub communication, Actions and Services and costum ROS Mess…☆34Aug 25, 2023Updated 3 years ago
- A common API for interfacing with secure services☆17Jul 10, 2026Updated 3 months ago
- STM32F103C8 MASTER and STM32F103RB Nucleo Board SLAVE☆10Oct 21, 2018Updated 8 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆31Dec 15, 2021Updated 4 years ago
- APB Logic☆29Sep 24, 2026Updated last month
- A set of Wishbone Controlled SPI Flash Controllers☆107Oct 31, 2022Updated 4 years ago
- Arena Allocator implementation in C☆13Jun 20, 2025Updated last year
- Simple single-port AXI memory interface☆51Jun 7, 2024Updated 2 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆48Apr 3, 2023Updated 3 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago