Simple UART transmitter and receiver
☆31Jun 11, 2019Updated 6 years ago
Alternatives and similar repositories for SystemVerilog-UART
Users that are interested in SystemVerilog-UART are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆18Apr 5, 2015Updated 11 years ago
- This is a detailed SystemVerilog course☆151Mar 4, 2025Updated last year
- SystemVerilog examples for a digital design course☆14Mar 30, 2021Updated 5 years ago
- UVM and System Verilog Manuals☆55Feb 11, 2019Updated 7 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆49Jun 19, 2020Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Must-have verilog systemverilog modules☆38May 1, 2022Updated 3 years ago
- Used for hardware trojan detection（Based on Trust_Hub）☆10Jul 30, 2019Updated 6 years ago
- UVM resource from github, run simulation use YASAsim flow☆33Apr 25, 2020Updated 5 years ago
- A RISC-V processor in system verilog☆12Jul 9, 2020Updated 5 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆18Aug 3, 2021Updated 4 years ago
- SystemVerilog modules and classes commonly used for verification☆57Jan 5, 2026Updated 3 months ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆42Jun 4, 2017Updated 8 years ago
- RISC-V Ibex core with Wishbone B4 interface☆21Apr 27, 2025Updated 11 months ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Jul 29, 2014Updated 11 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…☆13Oct 8, 2017Updated 8 years ago
- This repository contains a SystemVerilog implementation of a parametrized Round Robin arbiter with three instantiation options☆13Jan 28, 2024Updated 2 years ago
- Repository for system verilog labs from cadence☆15Feb 9, 2020Updated 6 years ago
- SystemVerilog examples and projects☆20Jun 10, 2025Updated 10 months ago
- Minimalistic RV32I RISC-V Processor in System Verilog☆26Sep 19, 2023Updated 2 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu☆14Apr 10, 2026Updated last week
- ☆22May 13, 2025Updated 11 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Jan 31, 2022Updated 4 years ago
- Fast TLB simulator for RISC-V systems☆16May 16, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆22Dec 17, 2021Updated 4 years ago
- The official Python library for the Log-hub API☆16Oct 27, 2025Updated 5 months ago
- ☆12Apr 12, 2026Updated last week
- ArduinoPWS is a full featured personal weather station☆11Aug 20, 2017Updated 8 years ago
- Support code for DVCon 2021 paper submission☆12Mar 1, 2021Updated 5 years ago
- ☆25Aug 10, 2023Updated 2 years ago
- the xoroshiro32++ and xoroshiro64++ PRNG algorthims by David Blackman and Sebastiano Vigna in C++, Verilog, VHDL and SpinalHDL.☆16Dec 2, 2018Updated 7 years ago
- AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…☆17Mar 22, 2017Updated 9 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Python-based domain-specific language for computational magnetism.☆13Updated this week
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆26Mar 8, 2026Updated last month
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆16Mar 26, 2026Updated 3 weeks ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆40Jun 24, 2020Updated 5 years ago
- To verify the SPI Master IP using the APB and SPI AVIPs☆22Apr 21, 2022Updated 3 years ago
- Wallace and Dadda tree multiplier generator in vhdl and verilog☆13Mar 14, 2026Updated last month
- An adapter board with pin headers for low-pin count (LPC) FPGA Mezzanine Cards (FMC).☆11Nov 2, 2020Updated 5 years ago