platformio / platform-shaktiLinks
Shakti: development platform for PlatformIO
☆31Updated 3 years ago
Alternatives and similar repositories for platform-shakti
Users that are interested in platform-shakti are comparing it to the libraries listed below
Sorting:
- FPGA250 aboard the eFabless Caravel☆30Updated 4 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆140Updated 2 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 8 months ago
- ☆64Updated 6 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆90Updated 6 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 6 years ago
- A simple three-stage RISC-V CPU☆24Updated 4 years ago
- Soft-microcontroller implementation of an ARM Cortex-M0☆26Updated 6 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆78Updated last year
- FPGA examples on Google Colab☆27Updated last year
- LunaPnR is a place and router for integrated circuits☆47Updated 2 weeks ago
- 32-bit RISC-V microcontroller☆11Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- ☆33Updated 9 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated 2 years ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆91Updated 5 months ago
- Drawio => VHDL and Verilog☆56Updated last year
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- RISC-V Nox core☆66Updated 2 weeks ago
- Flip flop setup, hold & metastability explorer tool☆36Updated 2 years ago
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆61Updated 4 months ago
- Spen's Official OpenOCD Mirror☆50Updated 5 months ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆11Updated 5 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆93Updated this week
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated last year
- Arduino compatible Risc-V Based SOC☆154Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated 3 weeks ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆78Updated this week
- ☆19Updated 2 months ago