platformio / platform-shakti
Shakti: development platform for PlatformIO
☆28Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for platform-shakti
- Content for the FPGA Primer Course offered by the OSFPGA Foundation, Redwood EDA, and VLSI System Design.☆25Updated last year
- A simple three-stage RISC-V CPU☆21Updated 3 years ago
- LunaPnR is a place and router for integrated circuits☆43Updated 3 months ago
- SoftCPU/SoC engine-V☆54Updated last year
- Spen's Official OpenOCD Mirror☆47Updated 8 months ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆34Updated 3 years ago
- Small footprint and configurable Inter-Chip communication cores☆54Updated last month
- A pipelined RISC-V processor☆47Updated 11 months ago
- Reusable Verilog 2005 components for FPGA designs☆36Updated last year
- The multi-core cluster of a PULP system.☆56Updated last week
- SAR ADC on tiny tapeout☆34Updated this week
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆35Updated last year
- M-extension for RISC-V cores.☆22Updated 3 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆29Updated 4 years ago
- ☆32Updated this week
- Naive Educational RISC V processor☆71Updated 3 weeks ago
- FPGA250 aboard the eFabless Caravel☆27Updated 3 years ago
- Zero to ASIC group submission for MPW2☆13Updated last year
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆40Updated 11 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆60Updated 7 months ago
- ☆36Updated 2 years ago
- ☆32Updated last week
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆62Updated last week
- Projects published on controlpaths.com and hackster.io☆39Updated 2 years ago
- Virtual development board for HDL design☆39Updated last year
- RV32I single cycle simulation on open-source software Logisim.☆16Updated 2 years ago