Alternatives and similar repositories for platform-shakti

Users that are interested in platform-shakti are comparing it to the libraries listed below

• hamsternz / simple-riscv
  A simple three-stage RISC-V CPU
  ☆23Updated 4 years ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆56Updated 6 months ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆87Updated 5 years ago
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆90Updated 3 months ago
• riscv-software-src / riscv-ctg
  ☆42Updated 7 months ago
• aniketnk / circular-queue-verilog
  Implementation of a circular queue in hardware using verilog.
  ☆17Updated 6 years ago
• iammituraj / pqr5asm
  PQR5ASM is a RISC-V Assembler compliant with RV32I
  ☆19Updated 2 months ago
• antmicro / renode-verilator-integration
  This repository contains sample code integrating Renode with Verilator
  ☆19Updated last month
• riscv-software-src / riscv-isac
  ☆33Updated 7 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last year
• openhwgroup / riscv-ovpsim-corev
  ☆11Updated last year
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆77Updated 2 years ago
• semidynamics / OpenVectorInterface
  Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
  ☆37Updated 3 years ago
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆61Updated 3 weeks ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆66Updated 4 months ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆54Updated 2 weeks ago
• merledu / azadi-soc
  Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
  ☆32Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆67Updated last year
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆35Updated 4 years ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 7 months ago
• os-fpga / GettingStartedWithFPGAs
  Content for the FPGA Primer Course offered by the OSFPGA Foundation, Redwood EDA, and VLSI System Design.
  ☆34Updated last year
• zeeshanrafique23 / mdu
  M-extension for RISC-V cores.
  ☆31Updated 7 months ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆50Updated 3 months ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆60Updated 7 months ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆43Updated 3 weeks ago
• klessydra / T13x
  An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …
  ☆46Updated 10 months ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆59Updated last month
• PeterAaser / tdt4255-chisel-intro
  ☆26Updated 4 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆57Updated 5 years ago