t-hishinuma / DD-AVX_v3
Library of High Precision Sparse Matrix Operations Accelerated by SIMD
☆42Updated 3 years ago
Alternatives and similar repositories for DD-AVX_v3:
Users that are interested in DD-AVX_v3 are comparing it to the libraries listed below
- This is the git repository for RIKEN simulator designed to simulate the binary code for Fujitsu A64FX.☆36Updated 4 years ago
- NLCPy : NumPy-like API accelerated with SX-Aurora TSUBASA☆15Updated last year
- Describe stencil formurae without even translating them☆58Updated 8 years ago
- ☆51Updated 4 years ago
- ASM generation tool for GAS/NASM/MASM with Xbyak-like syntax in Python☆12Updated last month
- monolish: MONOlithic LInear equation Solvers for Highly-parallel architecture☆200Updated last month
- instruction-bench☆36Updated 2 years ago
- Base container for developing C++ and Fortran HPC applications☆18Updated 2 years ago
- Quantum Computer Simulator☆22Updated 2 years ago
- WIP: 一週間でなれる!スパコンプログラマ Rust版☆25Updated 3 years ago
- WIP: 一週間でなれる!スパコンプログラマ Rust版☆38Updated 3 years ago
- A SYCL Implementation for CPU and SX-Aurora TSUBASA☆52Updated 2 years ago
- ネ ットワーク系演習II:ハイパフォーマンスコンピューティング☆62Updated 4 months ago
- Armv8 A64 Assembly & Intrinsics Guide Server☆25Updated last year
- repository to share the quantum information and quantum computer articles☆67Updated 5 years ago
- Qgate, Quntum circuit simulator☆31Updated 4 years ago
- ☆43Updated 3 weeks ago
- ☆22Updated 2 months ago
- kv - a C++ Library for Verified Numerical Computation☆87Updated last month
- ☆63Updated last year
- Write RISC-V CPU in Veryl☆31Updated 3 weeks ago
- Omni Compiler for C and Fortran programs with XcalableMP and OpenACC directives☆61Updated last year
- OpenJij : Framework for the Ising model and QUBO.☆103Updated this week
- Describe stencil formurae without even translating them☆16Updated 5 years ago
- 常微分方程式の数値解法の基礎.(教材)☆22Updated 7 years ago
- C++ library for a binary quadratic model☆14Updated 3 weeks ago
- OpenCL backend for CuPy☆153Updated 4 years ago
- ☆28Updated 2 years ago
- Open source RISC-V IP core for FPGA/ASIC design☆30Updated 9 months ago
- Zenn contents☆11Updated 3 weeks ago