riscv-non-isa / server-soc
The repo holds the draft non-ISA Server SoC specification being developed by the Server SoC specification TG and to release intermediate releases of the specification on milestones. Further downstream this repo will be used to release specifications for public review.
☆19Updated this week
Related projects: ⓘ
- RISC-V IOMMU Specification☆84Updated last week
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆71Updated last month
- ☆76Updated 2 years ago
- Open-source high-performance non-blocking cache☆63Updated this week
- ☆71Updated 2 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆61Updated 2 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆84Updated 3 weeks ago
- CVA6 SDK containing RISC-V tools and Buildroot☆59Updated 2 months ago
- ☆27Updated 2 months ago
- ☆40Updated 3 months ago
- ☆72Updated 3 weeks ago
- ☆80Updated 3 weeks ago
- pulp_soc is the core building component of PULP based SoCs☆76Updated last month
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 3 months ago
- AIA IP compliant with the RISC-V AIA spec☆26Updated 3 weeks ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆161Updated last month
- The multi-core cluster of a PULP system.☆55Updated this week
- ☆39Updated 2 years ago
- Open-source non-blocking L2 cache☆31Updated this week
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 4 years ago
- Self checking RISC-V directed tests☆75Updated last week
- RiscyOO: RISC-V Out-of-Order Processor☆148Updated 4 years ago
- Provides dot visualizations of chisel/firrtl circuits☆114Updated last year
- RISC-V Architecture Profiles☆104Updated 2 weeks ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆86Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆58Updated 3 weeks ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆26Updated 4 months ago
- RISC-V architecture concurrency model litmus tests☆68Updated 11 months ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆143Updated 2 years ago
- ☆60Updated 3 years ago