An ASCII Header Generator for Network Protocols
☆14Dec 12, 2024Updated last year
Alternatives and similar repositories for protocol
Users that are interested in protocol are comparing it to the libraries listed below
Sorting:
- Language for simplifying parameterized RTL design☆12Nov 6, 2024Updated last year
- ☆11Jul 4, 2016Updated 9 years ago
- Open SoC Debug Hardware Reference Implementation☆16Jul 15, 2019Updated 6 years ago
- ☆11Nov 24, 2020Updated 5 years ago
- Translates the DSD/DSF file into WAV file written in C for learning,☆11Feb 21, 2019Updated 7 years ago
- 利用扩展卡尔曼滤波进行姿态解算☆14Dec 8, 2015Updated 10 years ago
- Basic board manager with WiFi AP / STA mode, HTTP server and firmware OTA update☆11May 31, 2021Updated 4 years ago
- Generated files from ANTLR4 for Verilog parsing in Python☆12Jul 12, 2022Updated 3 years ago
- USB1.1 Host Controller + PHY☆15Aug 4, 2021Updated 4 years ago
- Simulink model for noise shaping SAR ADC☆12Mar 17, 2020Updated 5 years ago
- This software pack enables developers to develop and deploy neural networks on MCU-based systems for building smart sensing applications.…☆16Jul 30, 2024Updated last year
- Sample Linux kernel modules☆14Aug 13, 2013Updated 12 years ago
- A simple PDM microphone interface on FPGA☆14Jan 16, 2022Updated 4 years ago
- Verification of Ethernet Switch System Verilog☆11Oct 21, 2016Updated 9 years ago
- This is a tool to login qq zone using python, with multithreads to scrapy what you want,such as, message, blogs board, and photos.☆10May 11, 2017Updated 8 years ago
- Linux development repository for socfpga☆14Feb 25, 2026Updated last week
- HiSilicon ip camera SoCs SystemRDL registers description☆12Oct 18, 2023Updated 2 years ago
- Digital Standard Cells based SAR ADC☆14Aug 5, 2021Updated 4 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- riscv64 opensbi baremetal☆11Jan 4, 2021Updated 5 years ago
- This is a demo for still image compression application☆14Apr 14, 2018Updated 7 years ago
- Hardware Description Language Translator☆17Feb 28, 2026Updated last week
- SystemVerilog Constraint Layering via Reusable Randomization Policy Classes Examples☆17Mar 8, 2015Updated 11 years ago
- 深度学习500问，以问答形式对常用的概率知识、线性代数、机器学习、深度学习、计算机视觉等热点问题进行阐述，以帮助自己及有需要的读者。 全书分为15个章节，近20万字。由于水平有限，书中不妥之处恳请广大读者批评指正。 未完待续............ 如有意合作，联系sc…☆15Oct 28, 2018Updated 7 years ago
- Processor support packages☆19Feb 2, 2021Updated 5 years ago
- UVM verification kits which uses YASA as simulation script☆17Dec 10, 2019Updated 6 years ago
- Tiny bootloader for embedded devices, optimised for ease of porting☆21Sep 4, 2018Updated 7 years ago
- Altium Designer Common Components☆16Mar 14, 2022Updated 3 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Jul 23, 2019Updated 6 years ago
- ☆19Nov 20, 2017Updated 8 years ago
- ☆20Nov 7, 2019Updated 6 years ago
- The Ultra-Low Power RISC Core☆15May 5, 2020Updated 5 years ago
- verilator testbench w/ Javascript using N-API☆18Feb 19, 2026Updated 2 weeks ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Feb 21, 2020Updated 6 years ago
- This is a python repo for flattening Verilog☆20Dec 19, 2025Updated 2 months ago
- Documentation for Digital Design course☆20Jun 10, 2025Updated 8 months ago
- Source code repo for UVM Tutorial for Candy Lovers☆14Apr 23, 2017Updated 8 years ago
- MATLAB Vision HDL☆16Jan 17, 2020Updated 6 years ago
- understanding of cocotb （In Chinese Only）☆21Jun 10, 2025Updated 8 months ago