AI-assisted FPGA development across AMD Vivado, Anlogic TangDynasty, and Intel Quartus.
☆56Aug 17, 2026Updated 2 months ago
Alternatives and similar repositories for SynthPilot
Users that are interested in SynthPilot are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Vivado MCP server — 让 Claude Code / Cursor / Codex 驱动本地 FPGA 全流程。30 个精选工具、8 个证据驱动 Prompt、doctor 环境自检、GUI/Tcl/attach 会话，以及时序和 CRITICAL WAR…☆164Sep 22, 2026Updated last month
- FPGA hardware design guide based on real-world projects. Covers SystemVerilog, Vivado workflow, timing closure, CDC handling, and Xilin…☆20Feb 6, 2026Updated 8 months ago
- SynthPilot官方教程文档☆34Apr 8, 2026Updated 6 months ago
- MCP server that holds vivado and allows access to vivado without starting a new batch command every time☆67Feb 19, 2026Updated 8 months ago
- Scalable FPGA General-Purpose Open-Source Toolchain☆108Mar 30, 2026Updated 7 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- FPL'26 Optimization Contest☆55Sep 15, 2026Updated last month
- Xilinx/AMD FPGA & MPSoC Vivado design skill for Claude — covers block design, IP config, XDC constraints, synthesis, implementation and b…☆479Apr 25, 2026Updated 6 months ago
- ☆221Oct 23, 2026Updated last week
- ☆180Sep 5, 2026Updated last month
- Joker TV (USB) FPGA verilog/vhdl code☆16May 19, 2026Updated 5 months ago
- AES RoCC Accelerator☆10May 20, 2021Updated 5 years ago
- AI-powered MATLAB-to-HLS framework for WLAN 802.11 synchronization. 3.88x fewer LUTs than HDL Coder on Zynq-7020.☆14Feb 5, 2026Updated 8 months ago
- 基于FPGA进行车牌识别☆126Oct 19, 2023Updated 3 years ago
- xk264：AVC/H.264 Video Encoder IP Core (RTL)☆68Mar 22, 2023Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ESP32S3-16M，LVGL，platform，lyrics speaker☆12Sep 9, 2023Updated 3 years ago
- FFT algorithm for fpga☆26Aug 17, 2021Updated 5 years ago
- Matrix Multiplication in Hardware☆17Jun 3, 2020Updated 6 years ago
- ☆32Jul 30, 2025Updated last year
- This is the repository for a verilog implementation of a lzrw1 compression core☆20Dec 8, 2017Updated 8 years ago
- Vivado HLS study notes, courses, documents.☆13Dec 7, 2019Updated 6 years ago
- ☆23Jun 28, 2022Updated 4 years ago
- Display Stream Compression 1.2a☆17Oct 18, 2023Updated 3 years ago
- Classify modulation of signals☆16Jan 16, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- SystemVerilog AXI verification library and video-DMA IP: AXI4/Lite/Stream BFMs, triple-buffer VDMA, and multi-tap temporal VDMA with byte…☆30Jul 5, 2026Updated 3 months ago
- Verilog Ethernet components for FPGA implementation☆26Jun 26, 2023Updated 3 years ago
- This reposotory is for a project about Distributed TDMA for Mobile UWB Network Localization☆18Jun 1, 2021Updated 5 years ago
- 将 Verilog 设计规范、流水线模式与 FPGA 优化笔记结构化为可查询的本地知识库，供本地智能代理或脚本检索并返回带出处的实现建议与示例代码。☆27May 23, 2026Updated 5 months ago
- Bitstream Embedded RAM Transfusion☆11Aug 4, 2021Updated 5 years ago
- 基于FPGA的FFT☆19Feb 18, 2019Updated 7 years ago
- An LSTM template and a few examples using Vivado HLS☆48May 4, 2024Updated 2 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated last year
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆21Aug 14, 2026Updated 2 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Vivado MCP Server — AI 驱动的 FPGA 开发助手，自动诊断 CRITICAL WARNING 并给出修复建议☆26Mar 12, 2026Updated 7 months ago
- few python scripts to clone all IP cores from opencores.org☆32Jan 8, 2024Updated 2 years ago
- An Automatic Framework to Optimize Sparse Triangular Solve on GPUs☆12Aug 20, 2024Updated 2 years ago
- Agent skill for Verilog-2001 RTL generation and FPGA design workflows.☆323Aug 25, 2026Updated 2 months ago
- ☆12May 29, 2020Updated 6 years ago
- 基于FPGA-Pynq的车牌识别系统。The LPR system of FPGA-Pynq☆13Mar 22, 2019Updated 7 years ago
- 轻量级跨平台 Verilog 仿真工程管理器，支持 Node cli 和 VS Code 扩展☆16Oct 16, 2026Updated 2 weeks ago