🏆 Amazon Best Seller | Full-stack AI NPU Design (Python, Verilog, ISA, FPGA) Vol.2 Coming Soon!
☆27Mar 3, 2026Updated 5 months ago
Alternatives and similar repositories for AI_NPU_System_Design_v1
Users that are interested in AI_NPU_System_Design_v1 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆16Updated this week
- KV260 integration lane for PCCX™ v002 LLM IP-core bring-up, validation, and board/runtime evidence.☆17Jun 3, 2026Updated 2 months ago
- A basic documentation generator for Verilog, similar to Doxygen.☆13Aug 5, 2016Updated 10 years ago
- Example Projects for the Microsemi SmartFusion 2☆11Dec 10, 2017Updated 8 years ago
- Neural Network Decoders for Quantum Error Correcting Codes☆37Jan 17, 2018Updated 8 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Very tiny TOML parser in C☆28Nov 10, 2025Updated 9 months ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- ☆31Jun 13, 2021Updated 5 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆35Oct 15, 2024Updated last year
- Reverse Engineering of the Cisco HWIC-3G-CDMA PCB☆48Mar 7, 2024Updated 2 years ago
- JESD204b modules in VHDL☆31Apr 18, 2019Updated 7 years ago
- Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV☆12Aug 9, 2026Updated 3 weeks ago
- Support code for DVCon 2021 paper submission☆13Mar 1, 2021Updated 5 years ago
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Apr 6, 2023Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆19Updated this week
- ☆10Dec 15, 2023Updated 2 years ago
- ☆10Nov 2, 2023Updated 2 years ago
- Latest in the line of the E32 processors with better/generic cache placement☆10Feb 25, 2023Updated 3 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆35Feb 2, 2026Updated 6 months ago
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Jul 14, 2026Updated last month
- A curated list of FMCW-LiDAR papers and resources.☆39May 19, 2026Updated 3 months ago
- ☆10Dec 17, 2025Updated 8 months ago
- ☆11Apr 5, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- List of several designs I have been working through the years to avoid re-designing it again☆16Jun 17, 2024Updated 2 years ago
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 3 years ago
- ☆15May 17, 2025Updated last year
- ☆15May 24, 2025Updated last year
- Provides automation scripts for building BFMs☆16Apr 19, 2025Updated last year
- Formal Verification of RISC V IM Processor☆11Mar 27, 2022Updated 4 years ago
- ESnet general-purpose FPGA design library.☆14Updated this week
- vector accelerating unit☆37Dec 1, 2020Updated 5 years ago
- SoC based on RISC V ISA☆10Apr 22, 2022Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- ☆11Aug 16, 2019Updated 7 years ago
- The HeLiPR Pointcloud Toolbox is a sophisticated software suite tailored for processing and analyzing the HeLiPR (Heterogeneous LiDAR Pla…☆46Aug 30, 2024Updated 2 years ago
- Designing a Multi-Agent Fabric Integration Architecture to run on de10-lite FPGA.☆19Apr 28, 2026Updated 4 months ago
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- ☆12Mar 16, 2026Updated 5 months ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- ☆14Jun 4, 2025Updated last year