mediaic / Crash_Course_for_New_MembersLinks
Deep Learning & VLSI Crash Course for New Members
☆40Updated 6 months ago
Alternatives and similar repositories for Crash_Course_for_New_Members
Users that are interested in Crash_Course_for_New_Members are comparing it to the libraries listed below
Sorting:
- EE 260 Winter 2017: Advanced VLSI Design☆67Updated 9 years ago
- RTL + Synthesis + APR☆11Updated 6 months ago
- Generator of verilog description for FPGA MobileNet implementation☆183Updated 3 years ago
- Verilog Convolutional Neural Network on PYNQ☆28Updated 7 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆55Updated 8 years ago
- Systolic-array based Deep Learning Accelerator generator☆28Updated 5 years ago
- Computer-Aided VLSI System Design☆23Updated last year
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆14Updated 6 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆20Updated 7 years ago
- ☆66Updated 3 years ago
- A convolutional neural network implemented in hardware (verilog)☆166Updated 8 years ago
- Simple RiscV core for academic purpose.☆23Updated 5 years ago
- UVM and System Verilog Manuals☆48Updated 6 years ago
- Discussion Forum for High-Level Synthesis (HLS) Courses in Taiwan.☆56Updated 2 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆149Updated 6 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆120Updated 5 years ago
- ☆46Updated 5 years ago
- Tutorials on HLS Design☆51Updated 6 years ago
- This repository contains source code for past labs and projects involving FPGA and Verilog based designs☆120Updated 6 years ago
- A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL☆94Updated 6 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆144Updated 3 years ago
- ☆27Updated 6 years ago
- OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.☆82Updated 2 years ago
- Implementing Different Adder Structures in Verilog☆74Updated 6 years ago
- Courseworks of CS6165 VLSI Physical Design Automation, NTHU.☆50Updated 5 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19Updated 7 years ago
- Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)☆38Updated 4 years ago
- ☆45Updated 2 years ago
- Learn systemC with examples☆130Updated 3 years ago
- A hardware implementation of a feed-forward Convolutional Neural Network called XNOR-Net which has faster execution due to the replacemen…☆17Updated 7 years ago