Alternatives and similar repositories for Crash_Course_for_New_Members:

Users that are interested in Crash_Course_for_New_Members are comparing it to the libraries listed below

• zli87 / Integrated_Circuit_Design_Laboratory_IC_Lab
  Integrated Circuit Design Laboratory(IC Lab) at 2019 Fall, NCTU. Final project is a customized 16 bits ISA processor.
  ☆20Updated 3 years ago
• mediaic / VLSI_Lab1
  RTL + Synthesis + APR
  ☆11Updated last year
• max2468tw / IC_Lab
  NCTU 2018 Spring Integrated Circuit Design Laboratory
  ☆24Updated 6 years ago
• Ni-ChiTing / IC_contest_cell_based_design
  ☆11Updated 3 years ago
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆60Updated 8 years ago
• derek8955 / ic_contest
  IC Contest
  ☆28Updated last year
• g0kul / vcnn
  Verilog Convolutional Neural Network on PYNQ
  ☆28Updated 6 years ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆51Updated 5 years ago
• prateek22sri / XNOR-net-Binary-connect
  A hardware implementation of a feed-forward Convolutional Neural Network called XNOR-Net which has faster execution due to the replacemen…
  ☆18Updated 6 years ago
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆17Updated 6 years ago
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆90Updated 4 years ago
• Daikon-Sun / Physical-Design-for-Nanometer-ICs
  Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)
  ☆39Updated 6 years ago
• albertfan1120 / NTU_CVSD_2021
  Computer-Aided VLSI System Design
  ☆17Updated 3 months ago
• jgoeders / dac_sdc_2021
  ☆23Updated 3 years ago
• tharunchitipolu / Dadda-Multiplier-using-CSA
  Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
  ☆34Updated 8 months ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆45Updated last month
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆50Updated 7 years ago
• xiangze / CNN_FPGA
  verilog CNN generator for FPGA
  ☆34Updated 4 years ago
• lukasc-ch / ExtendedBitPlaneCompression
  Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…
  ☆17Updated 5 years ago
• Xilinx / Vitis-In-Depth-Tutorial
  ☆116Updated 3 years ago
• hankshyu / ICLab-2023
  Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)
  ☆104Updated 5 months ago
• maeri-project / MAERI_bsv_isca2018
  MAERI public release
  ☆31Updated 3 years ago
• EECS-NTNU / bismo
  BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
  ☆132Updated 5 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 4 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆63Updated last week
• yutongshen / RISC-V_SoC
  ☆35Updated last year
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆25Updated 4 years ago
• asfhiolNick / NTU_CVSD_202201
  楊家驤老師的"電腦輔助積體電路系統設計"作業(CVSD)
  ☆29Updated 4 months ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 9 months ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆47Updated 4 years ago