mediaic / Crash_Course_for_New_Members

Related projects ⓘ

Alternatives and complementary repositories for Crash_Course_for_New_Members

• max2468tw / IC_Lab
  NCTU 2018 Spring Integrated Circuit Design Laboratory
  ☆24Updated 6 years ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆49Updated 4 years ago
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆58Updated 7 years ago
• mediaic / VLSI_Lab1
  RTL + Synthesis + APR
  ☆11Updated last year
• Ni-ChiTing / IC_contest_cell_based_design
  ☆10Updated 3 years ago
• maao666 / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆24Updated 3 years ago
• learnwithexamples / learnsystemc
  Learn systemC with examples
  ☆95Updated last year
• zli87 / Integrated_Circuit_Design_Laboratory_IC_Lab
  Integrated Circuit Design Laboratory(IC Lab) at 2019 Fall, NCTU. Final project is a customized 16 bits ISA processor.
  ☆19Updated 3 years ago
• The-OpenROAD-Project / yosys
  Logic synthesis and ABC based optimization
  ☆46Updated last week
• brianhill11 / FPGA-CNN
  This repo is for ECE44x (Fall2015-Spring2016)
  ☆19Updated 6 years ago
• aasthadave9 / Advanced-Physical-Design-Using-OpenLANE-Sky130
  This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…
  ☆14Updated 3 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆54Updated 4 years ago
• g0kul / vcnn
  Verilog Convolutional Neural Network on PYNQ
  ☆27Updated 6 years ago
• pulp-platform / pulp-nn
  ☆76Updated last year
• 4a1c0 / RV32i-Verilog
  Simple RiscV core for academic purpose.
  ☆22Updated 4 years ago
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆35Updated 5 years ago
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆46Updated 7 years ago
• sh-vlad / FPGA_rtime_HDR_video
  We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.
  ☆31Updated 5 years ago
• hankshyu / ICLab-2023
  Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)
  ☆88Updated 2 months ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆44Updated 3 months ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 6 months ago
• tharunchitipolu / Dadda-Multiplier-using-CSA
  Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
  ☆34Updated 5 months ago
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆12Updated 3 years ago
• PacoReinaCampo / SoC-DV
  System on Chip verified with UVM/OSVVM/FV
  ☆23Updated 2 weeks ago
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆15Updated 6 years ago
• twweeb / VLSI-Physical-Design-Automation
  Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
  ☆42Updated 3 years ago
• xiangze / CNN_FPGA
  verilog CNN generator for FPGA
  ☆32Updated 3 years ago
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆22Updated 3 months ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆59Updated 3 years ago