mediaic / VLSI_Lab1Links
RTL + Synthesis + APR
☆11Updated last week
Alternatives and similar repositories for VLSI_Lab1
Users that are interested in VLSI_Lab1 are comparing it to the libraries listed below
Sorting:
- Deep Learning & VLSI Crash Course for New Members☆39Updated last week
- ☆9Updated last year
- NCTU 2018 Spring Integrated Circuit Design Laboratory☆24Updated 7 years ago
- RTL + Verfication + Synthesis + APR☆11Updated 7 years ago
- ☆11Updated 2 years ago
- first-order deep learning accelerator model☆18Updated 7 years ago
- Verilog Implementation of 32-bit Floating Point Adder☆40Updated 5 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆22Updated 4 years ago
- ☆4Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 5 months ago
- ☆72Updated 2 years ago
- ☆10Updated 2 years ago
- MAERI public release☆31Updated 3 years ago
- Template for project1 TPU☆19Updated 4 years ago
- This repo is "NTHU VLSI System Design and Implementation" course project.☆13Updated 8 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆34Updated last year
- ☆13Updated 4 years ago
- Docker container with tools for the Timeloop/Accelergy tutorial☆22Updated last year
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆20Updated 5 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆198Updated 5 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Updated 4 years ago
- ☆71Updated 5 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆141Updated 5 years ago
- Tutorials on HLS Design☆52Updated 5 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network☆43Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- Neural Network Evaluation Tool on Crossbar-based Accelerator with Resistive Memory☆40Updated 5 years ago