bol-edu / HLS-SOC-DiscussionsLinks
Discussion Forum for High-Level Synthesis (HLS) Courses in Taiwan.
☆54Updated 2 years ago
Alternatives and similar repositories for HLS-SOC-Discussions
Users that are interested in HLS-SOC-Discussions are comparing it to the libraries listed below
Sorting:
- IC Contest☆41Updated 2 years ago
- ☆14Updated 4 years ago
- Computer-Aided VLSI System Design☆21Updated 11 months ago
- ☆19Updated 2 years ago
- Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)☆136Updated last year
- ☆33Updated last year
- Convolutional accelerator kernel, target ASIC & FPGA☆226Updated 2 years ago
- ☆10Updated last year
- NCTU 2018 Spring Integrated Circuit Design Laboratory☆24Updated 7 years ago
- ☆19Updated 5 months ago
- 紀錄一下自己寫過的所有Lab☆35Updated last year
- IC implementation of TPU☆132Updated 5 years ago
- IC implementation of Systolic Array for TPU☆278Updated 11 months ago
- ☆38Updated 2 years ago
- [NYCU 2021 Spring] Digital Circuits and Systems☆20Updated last year
- 3×3脉动阵列乘法器☆47Updated 6 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆161Updated last year
- IC-contest 2012~2024☆20Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆175Updated 3 weeks ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆52Updated 8 years ago
- Small-scale Tensor Processing Unit built on an FPGA☆202Updated 6 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆168Updated 5 years ago
- 交通大學iclab 2023 fall☆42Updated 11 months ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆44Updated 2 years ago
- 超詳細 ICLAB 2024 Spring 修課心得 & 修課指南,含資源整理☆99Updated 5 months ago
- Implement a bitonic sorting network on FPGA☆46Updated 3 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆108Updated 2 months ago
- This is a verilog implementation of 4x4 systolic array multiplier☆59Updated 4 years ago
- NCTU 2021 Spring Integrated Circuit Design Laboratory☆187Updated 2 years ago