karanahujax / PUF
Cryptographic Key Generation from PUF Data
☆20Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for PUF
- Defense/Attack PUF Library (DA PUF Library)☆46Updated 4 years ago
- The first open source software-based Physically Unclonable Function (PUF) using off-the-shelf SRAM☆90Updated last month
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆21Updated 6 years ago
- FPGA implementation of a physical unclonable function for authentication☆32Updated 7 years ago
- Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs☆10Updated 4 years ago
- FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.☆15Updated 7 years ago
- Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.☆12Updated this week
- Python Code and Dataset for different PUFs☆16Updated 3 years ago
- The ML_Attack_XOR_PUF is a Machine Learning-based model for attacking the XOR Physical Unclonable Functions using a small number of chall…☆16Updated 4 years ago
- A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration☆29Updated 4 months ago
- Cryptanalysis of Physically Unclonable Functions☆79Updated 4 months ago
- A list of VHDL codes implementing cryptographic algorithms☆25Updated 2 years ago
- High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.☆43Updated last year
- Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field☆22Updated 7 years ago
- Repository to store all design and testbench files for Senior Design☆17Updated 4 years ago
- ☆45Updated 3 years ago
- ☆18Updated 2 years ago
- True Random Number Generator core implemented in Verilog.☆72Updated 4 years ago
- A true random number generator with ring oscillators structure written in VHDL targeting FPGA's.☆9Updated 4 years ago
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆15Updated 5 years ago
- NIST LWC Hardware Reference Implementation of Ascon v1.2☆24Updated last year
- Hardware implementation of polynomial multiplication operation of CRYSTALS-KYBER PQC scheme☆25Updated 2 years ago
- VexRiscv reference platforms for the pqriscv project☆15Updated 8 months ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆46Updated 6 years ago
- ☆20Updated 5 years ago
- VHDL Implementation of AES Algorithm☆72Updated 3 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆21Updated last month
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆37Updated 7 years ago
- AES hardware engine for Xilinx Zynq platform☆28Updated 3 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆17Updated 7 years ago