Alternatives and similar repositories for soc-fpga2sdram-test

Users that are interested in soc-fpga2sdram-test are comparing it to the libraries listed below

• OpenDGPS / zynq-axi-dma-sg
  Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020
  ☆56Updated 8 years ago
• MIPSfpga / mipsfpga-plus
  MIPSfpga+ allows loading programs via UART and has a switchable clock
  ☆111Updated 6 years ago
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆86Updated 2 years ago
• imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
  This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…
  ☆72Updated 8 years ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆35Updated 4 years ago
• olofk / observer
  ☆43Updated 5 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆123Updated 2 years ago
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆39Updated 5 years ago
• twlostow / urv-core
  uRV RISC-V core
  ☆18Updated 10 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆68Updated 3 years ago
• tmbinc / xvcd
  Xilinx Virtual Cable Daemon
  ☆124Updated 10 months ago
• enjoy-digital / daisho
  Test of the USB3 IP Core from Daisho on a Xilinx device
  ☆100Updated 6 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆35Updated 7 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆48Updated 5 years ago
• RISCV-on-Microsemi-FPGA / SoftConsole
  Eclipse based IDE for RISC-V bare metal software development.
  ☆20Updated 6 years ago
• AnttiLukats / HackaZynq
  Open Source ZYNQ Board
  ☆31Updated 10 years ago
• CospanDesign / nysa-sata
  ☆89Updated 8 years ago
• hamsternz / FPGA_GigabitTx
  Sending UDP packets out over a Gigabit PHY with an FPGA.
  ☆44Updated 9 years ago
• PyHDI / zynq-linux
  How to configure Debian Linux environment for Xilinx Zynq.
  ☆32Updated 9 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago
• hamsternz / ArtyEtherentTX
  Sending raw data from the Digilent Arty FPGA board
  ☆25Updated 9 years ago
• syntacore / scr1-sdk
  open-source SDKs for the SCR1 core
  ☆76Updated last year
• skristiansson / i2s
  i2s core, with support for both transmit and receive
  ☆32Updated 7 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated 2 years ago
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆85Updated 2 years ago
• jsyk / miilink
  Connecting FPGA and MCU using Ethernet RMII
  ☆23Updated 9 years ago
• FPGAwars / FPGA-peripherals
  Collection of open-source peripherals in Verilog
  ☆183Updated 3 years ago
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆86Updated last year