Alternatives and similar repositories for soc-fpga2sdram-test

Users that are interested in soc-fpga2sdram-test are comparing it to the libraries listed below

• twlostow / urv-core
  uRV RISC-V core
  ☆18Updated 10 years ago
• tmbinc / xvcd
  Xilinx Virtual Cable Daemon
  ☆125Updated 7 months ago
• enjoy-digital / daisho
  Test of the USB3 IP Core from Daisho on a Xilinx device
  ☆100Updated 6 years ago
• MIPSfpga / mipsfpga-plus
  MIPSfpga+ allows loading programs via UART and has a switchable clock
  ☆111Updated 6 years ago
• imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
  This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…
  ☆69Updated 8 years ago
• OpenDGPS / zynq-axi-dma-sg
  Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020
  ☆56Updated 8 years ago
• RISCV-on-Microsemi-FPGA / SoftConsole
  Eclipse based IDE for RISC-V bare metal software development.
  ☆20Updated 5 years ago
• derekmulcahy / xvcpi
  Xilinx Virtual Cable Server for Raspberry Pi
  ☆118Updated 3 years ago
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆87Updated 2 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆120Updated last year
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆34Updated 7 years ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆35Updated 4 years ago
• iDoka / GOST-28147-89
  Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
  ☆17Updated last year
• quartiq / bscan_spi_bitstreams
  FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
  ☆56Updated 2 years ago
• CospanDesign / nysa-sata
  ☆87Updated 8 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆67Updated 9 months ago
• openXC7 / xc7k325t-blinky-nextpnr
  ☆45Updated 2 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆46Updated 5 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆64Updated 2 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆63Updated 6 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆52Updated 2 years ago
• olofk / observer
  ☆42Updated 5 years ago
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆32Updated 5 years ago
• im-tomu / valentyusb
  FPGA USB stack written in LiteX
  ☆129Updated 3 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆46Updated last year
• open-tool-forge / summon-fpga-tools
  A simple script to build open-source FPGA tools.
  ☆53Updated 3 years ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆65Updated 7 years ago
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆84Updated last year
• Xilinx / revCtrl
  Revision Control Labs and Materials
  ☆24Updated 7 years ago