Alternatives and similar repositories for timetoexplore

Users that are interested in timetoexplore are comparing it to the libraries listed below

• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆71Updated 3 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆82Updated 5 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆44Updated 2 weeks ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆93Updated 7 years ago
• MJoergen / HyperRAM
  Portable HyperRAM controller
  ☆62Updated last year
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆83Updated 5 years ago
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆34Updated 7 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆85Updated last year
• ldoolitt / vhd2vl
  ☆137Updated last year
• davidthings / tinyfpga_bx_usbserial
  USB Serial on the TinyFPGA BX
  ☆139Updated 4 years ago
• projf / fpgatools
  Tools for FPGA development.
  ☆49Updated 4 months ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆94Updated 3 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆68Updated 3 years ago
• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• nullobject / sdram-fpga
  A FPGA core for a simple SDRAM controller.
  ☆122Updated 4 years ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆70Updated 7 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆97Updated 5 years ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆44Updated 4 years ago
• open-design / riscv-soc-cores
  ☆41Updated 4 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 9 months ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆131Updated last year
• rajesh-s / axi_cheatsheet
  A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)
  ☆30Updated 7 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆123Updated 2 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆51Updated 9 months ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆125Updated 5 years ago
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆130Updated 3 years ago
• mattvenn / vga-clock
  Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
  ☆62Updated 4 years ago
• smunaut / iCE40linux
  Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker
  ☆103Updated 2 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆47Updated last year
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆63Updated 6 years ago