Alternatives and similar repositories for Verilog-Snippets:

Users that are interested in Verilog-Snippets are comparing it to the libraries listed below

• SubZer0811 / VLSI
  All the projects and assignments done as part of VLSI course.
  ☆18Updated 4 years ago
• vedic-partap / Computer-Organization-and-Architecture-LAB
  Solution to COA LAB Assgn, IIT Kharagpur
  ☆35Updated 6 years ago
• suoto / hdl_string_format
  VHDL package to provide C-like string formatting
  ☆15Updated 2 years ago
• ashishrana160796 / verilog-starter-tutorials
  Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
  ☆56Updated 4 years ago
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆25Updated 5 years ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆19Updated 10 months ago
• mnasser431998 / bfu_dif_fft_rtl
  The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor
  ☆13Updated last year
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆55Updated last year
• learn-cocotb / tutorial
  Complete tutorial code.
  ☆15Updated 9 months ago
• dallingham / verilog-mode-snippets
  A set of yasnippets for emacs that assist with SystemVerilog
  ☆11Updated 13 years ago
• avashist003 / SystemVerilog_Design_Verification
  Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog
  ☆23Updated 2 years ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆32Updated 8 years ago
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆16Updated 4 years ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆16Updated 9 months ago
• semiDESIgner / 50daysRTLcode
  ☆16Updated last year
• kunalg123 / sky130RTLDesignAndSynthesisWorkshop
  ☆11Updated 2 years ago
• RClabiisc / I2SRV32-V-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆26Updated 7 months ago
• kumarswamy12 / ROUTER-1-3
  verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL
  ☆12Updated 6 years ago
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆28Updated 5 years ago
• rooinasuit / AXI_to_SPI
  Designing means to communicate as an SPI master, being a part of AXI interface
  ☆17Updated last year
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated 2 weeks ago
• andres-mancera / ethernet_10ge_mac_SV_tb
  SystemVerilog testbench for an Ethernet 10GE MAC core
  ☆44Updated 8 years ago
• adibis / Interrupt_Controller
  An 8 input interrupt controller written in Verilog.
  ☆25Updated 12 years ago
• sarthak268 / Embedded_Logic_and_Design
  This repository contains all labs done as a part of the Embedded Logic and Design course.
  ☆23Updated 6 years ago
• sjaeckel / axi-bfm
  git clone of http://code.google.com/p/axi-bfm/
  ☆17Updated 11 years ago
• antoinemadec / uvm_code_gen
  Simple template-based UVM code generator
  ☆23Updated 2 years ago
• VerificationExcellence / verificationexcellence.github.io
  Verification Excellence Knowledge Sharing
  ☆21Updated 10 years ago
• sumanth-kalluri / 128-Bit-AES-Encryption-and-Decryption-in-Verilog
  This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.
  ☆22Updated 4 years ago
• mayurkubavat / SystemVerilog
  SystemVerilog examples and projects
  ☆17Updated 6 years ago
• mbits-mirafra / UVMCourse
  Structured UVM Course
  ☆38Updated last year