Synthesys-Lab / assassynLinks
Asynchronous semantics for architectural simulation and synthesis.
☆65Updated 2 weeks ago
Alternatives and similar repositories for assassyn
Users that are interested in assassyn are comparing it to the libraries listed below
Sorting:
- Virtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation met…☆81Updated 3 weeks ago
- ☆17Updated 10 months ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆33Updated last year
- A flexible, high-performance, user-friendly computer architecture simulator engine☆98Updated this week
- A fast, accurate, and easy-to-integrate memory simulator that model memory system performance with bandwidth--latency curves.☆31Updated 3 months ago
- WaferLLM: Large Language Model Inference at Wafer Scale☆88Updated last month
- ☆13Updated 9 months ago
- EQueue Dialect☆42Updated 4 years ago
- ☆52Updated last year
- Simulator code of the paper "Dissecting and Modeling the Architecture of Modern GPU Cores"☆60Updated 3 months ago
- ☆38Updated 7 months ago
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆39Updated last year
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆76Updated 5 months ago
- ☆26Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆65Updated last year
- ☆17Updated 3 months ago
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- ☆64Updated 3 years ago
- HeteroCL-MLIR dialect for accelerator design☆42Updated last year
- Artifact for paper "PIM is All You Need: A CXL-Enabled GPU-Free System for LLM Inference", ASPLOS 2025☆124Updated 9 months ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆19Updated last year
- ☆31Updated last week
- The wafer-native AI accelerator simulation platform and inference engine.☆49Updated last month
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆47Updated 3 years ago
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆28Updated last year
- ☆109Updated last year
- LLVM OpenCL C compiler suite for ventus GPGPU☆58Updated last month
- An alternative Vivado custom design example (to fully Vitis) for the User Logic Partition targeting VCK5000☆13Updated last year
- TileFlow is a performance analysis tool based on Timeloop for fusion dataflows☆66Updated last year
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆33Updated last year