Synthesys-Lab / assassyn
Asynchronous semantics for architectural simulation and synthesis.
☆17Updated this week
Alternatives and similar repositories for assassyn:
Users that are interested in assassyn are comparing it to the libraries listed below
- Being a full-stack hacker, RISCV, LLVM, and more.☆17Updated 3 years ago
- Yet another toy CPU.☆91Updated last year
- ☆14Updated last week
- This repo stores a more profound view of Computer Architecture: A Quantitative Approach that tells multi-tenancy, virtualize, fine graine…☆25Updated last year
- Virtuoso is a new simulator that focuses on modelling various memory management and virtual memory aspects.☆31Updated last year
- ☆18Updated last year
- HeteroRefactor: Refactoring for Heterogeneous Computing with FPGA☆10Updated 3 years ago
- Take your first step in writing a compiler. Implemented in Rust.☆15Updated last year
- ☆18Updated this week
- [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)☆14Updated 4 years ago
- 在RISC-V处理器上实现一个轻量级的Hypervisor。☆12Updated 4 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆26Updated 2 months ago
- A retargetable and extensible synthesis-based compiler for modern hardware architectures☆10Updated this week
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆13Updated 2 weeks ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆13Updated 4 months ago
- A Flexible Cache Architectural Simulator☆13Updated 3 months ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆27Updated last month
- BOOM's Simulation Accelerator.☆13Updated 3 years ago
- Run Rocket Chip on VCU128☆30Updated 4 months ago
- Recommended coding standard of Verilog and SystemVerilog.☆34Updated 3 years ago
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆30Updated this week
- Skyloft: A General High-Efficient Scheduling Framework in User Space (SOSP 2024)☆33Updated 6 months ago
- A Symmetric Multiprocessing OS Kernel over RISC-V☆30Updated 2 years ago
- Microarchitecture diagrams of several CPUs☆25Updated last week
- CPU micro benchmarks☆52Updated 2 weeks ago
- hardware & software prefetcher☆23Updated last year
- TiledKernel is a code generation library based on macro kernels and memory hierarchy graph data structure.☆19Updated 10 months ago
- ☆40Updated 2 months ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆16Updated 3 weeks ago