HUST-2022-组原课程设计：单周期CPU->支持动态分支预测的五段流水CPU+团队任务（2048）
☆15Dec 7, 2022Updated 3 years ago
Alternatives and similar repositories for HUST-riscv-CPU
Users that are interested in HUST-riscv-CPU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆21Jul 18, 2019Updated 6 years ago
- HUST-CS-2019 硬件综合训练-组原课设-riscv实现☆16Nov 3, 2022Updated 3 years ago
- 华中科技大学计算机组成原理课程设计☆33Dec 28, 2022Updated 3 years ago
- HUST-CS-2019 数据库系统原理及其实验☆22Oct 25, 2022Updated 3 years ago
- 华中科技大学操作系统实验 (Operating System lab of HUST) 包括课设内容☆19May 16, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- HUST-CS-2019 操作系统课程及其实验☆12Oct 26, 2022Updated 3 years ago
- 河南理工大学Educoder计算机组成原理实训☆15Jun 16, 2023Updated 2 years ago
- 2022WHU计算机系统综合设计 基于RISCV的五级流水线CPU Five stage CPU implement based on RISC-V☆12Oct 31, 2023Updated 2 years ago
- 2021级HUST操作系统实验以及操作系统课程设计实验和实验报告☆19Apr 21, 2024Updated 2 years ago
- 华中科技大学机器学习作业&课设. Solutions to HUST ML class tasks.☆87Nov 23, 2021Updated 4 years ago
- 乱序双发处理器，在2024年计算机系统能力大赛CPU赛道（龙芯杯）获二等奖，全国第四☆21Aug 20, 2024Updated last year
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 4 years ago
- 一生一芯RISCV处理器核代码仓库（包括相关工具）☆16Sep 11, 2024Updated last year
- A convolution based 3x3 GaussianBlur implementation using ARM NEON assembly engine☆10Jan 20, 2019Updated 7 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆25Mar 29, 2024Updated 2 years ago
- [NeurIPS'25] ContextAgent: Context-Aware Proactive LLM Agents with Open-World Sensory Perceptions☆41Dec 7, 2025Updated 5 months ago
- Tensor Processing Unit implementation in Verilog☆14Mar 18, 2025Updated last year
- 顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel☆29Jan 25, 2026Updated 4 months ago
- Verilog CAN controller that is compatible to the SJA 1000.☆16Apr 17, 2021Updated 5 years ago
- 国科大一生一芯第二期: RISCV-64 五级流水线CPU☆19Apr 17, 2021Updated 5 years ago
- 华中科技大学2020级编译原理educoder实验☆74Jun 5, 2023Updated 2 years ago
- 本项目实现的五子棋博弈游戏是基于AI的五子棋游戏。游戏模式可以分为人机对弈和双人对弈两种模式。本程序采用基于启发式max/min算法的alpha-beta 剪枝技术来选择出最佳的机器落子位置。除此之外，本项目还设置了残局闯关模式，在增加了游戏趣味性的同时给用户们带来了更好的游…☆10Jan 2, 2022Updated 4 years ago
- ☆11Jun 28, 2020Updated 5 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆14Nov 4, 2022Updated 3 years ago
- ☆30Nov 22, 2024Updated last year
- 华中科技大学计算机学院计算机组成原理实验☆13Jan 18, 2022Updated 4 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…☆14Mar 30, 2023Updated 3 years ago
- USB2.0 Device Controller IP Core☆16Aug 18, 2023Updated 2 years ago
- An Fusion of TMDB and Social media, So basically a social media application for Movie Lovers.☆17Mar 3, 2024Updated 2 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆14Jul 28, 2021Updated 4 years ago
- The code based on vLLM for the paper “ Cost-Efficient Large Language Model Serving for Multi-turn Conversations with CachedAttention”.☆11Sep 19, 2024Updated last year
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆18Feb 27, 2021Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- 华中科技大学CS文件存留，包含相关资料，代码以及报告☆163Apr 27, 2021Updated 5 years ago
- Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus☆16Oct 21, 2020Updated 5 years ago
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- 华中科技大学计算机学院20级实验报告/代码——汇编实验；机器学习；计算机系统基础；算法实验；游戏设计；组原；计算机网络；软件工程；数据库；计算机视觉；操作系统课设☆51Dec 16, 2023Updated 2 years ago
- Implementation of a cache memory in verilog☆15Dec 5, 2017Updated 8 years ago
- riscv指令集，单周期以及五级流水线CPU☆132Jan 6, 2025Updated last year
- hust-feiyue.github.io☆16Jan 1, 2021Updated 5 years ago