Alternatives and similar repositories for chisel-minicpu

Users that are interested in chisel-minicpu are comparing it to the libraries listed below

• NextMicon / NextMiconIDE
  🛠️ Graphical IDE for NextMicon
  ☆28Updated last year
• msyksphinz-self / swimmer_riscv
  Instruction set simulator for RISC-V
  ☆53Updated 4 years ago
• horie-t / homemade-riscv
  『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
  ☆13Updated 5 years ago
• icf3 / zevios
  original 8bit CPU of ICF3-Z
  ☆12Updated 5 years ago
• nananapo / veryl-riscv-book
  Let's write RISC-V CPU in Veryl!
  ☆46Updated 3 weeks ago
• ciniml / seccamp_riscv_cpu
  セキュリティ・キャンプ 2022-2024 RISC-V CPU自作ゼミ 資料置き場
  ☆37Updated 2 months ago
• msyksphinz-self / swimmer_rust
  RISC-V Simulator written in Rust
  ☆20Updated 5 years ago
• nlsynth / iroha
  Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
  ☆35Updated 3 years ago
• VLSI-JP / VLSI-JP.github.io
  ☆24Updated this week
• nlsynth / karuta
  Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…
  ☆105Updated 3 years ago
• moizumi99 / m99_riscv_emulator
  Simple RISC-V emulator
  ☆16Updated 4 years ago
• cpu-dev / cpu-dev.github.io
  ☆15Updated 5 years ago
• vaj / riscv-os
  A tiny educational OS for RISC-V
  ☆24Updated 8 months ago
• shibatchii / RISC-V
  RISC-V documentation transrate to Japanese.
  ☆73Updated 3 years ago
• kadomoto / poyo-v
  Open source RISC-V IP core for FPGA/ASIC design
  ☆31Updated 11 months ago
• Alignof / hikami
  A lightweight Type-1 hypervisor for RISC-V H-extension, featuring RISC-V extension emulation.
  ☆51Updated last week
• cpuex2019-yokyo / core
  RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo
  ☆13Updated 5 years ago
• lemolatoon / toy-shakyo
  ☆14Updated last year
• ciniml / seccamp_2022_riscv_cpu
  セキュリティキャンプ 2022 Y4 RISC-V CPU自作ゼミ 講義資料
  ☆29Updated 10 months ago
• nekomaru0510 / Violet
  ☆14Updated 2 months ago
• sugawara-bbbb / xv6-riscv-book
  Text describing xv6 on RISC-V
  ☆14Updated 4 years ago
• azrsh / azcc
  A toy C compiler, developed at seccamp2020.
  ☆21Updated last year
• msyksphinz-self / xv6_translate
  translation of XV6
  ☆49Updated 6 years ago
• panda5mt / KyogenRV
  The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
  ☆45Updated 4 years ago
• virtualsecureplatform / V2TT
  This is the repository for the transpiler to compile Verilog to C++ code with TFHE library.
  ☆18Updated 5 years ago
• kazunori279 / CPU32
  Tiny MIPS for Terasic DE0
  ☆35Updated 11 years ago
• sozysozbot / 2kmcc
  ☆28Updated 2 years ago
• kamiyaowl / rv32i-sim
  RISC-V Software Simulation
  ☆20Updated 6 years ago
• alphaKAI / cr0cd
  CR0.CD manipulate Linux Kernel Module as a proc filesystem
  ☆19Updated 5 years ago
• i4kimura / chip_architect
  Translation of http://chip-architect.com/news/2003_09_21_Detailed_Architecture_of_AMDs_64bit_Core.html
  ☆11Updated 6 years ago