jefferie / digital_recognition
利用ov5640摄像头采集图像,利用4.3寸RGB屏显示捕获到的数字,并将识别到的数字显示在数码管上。
☆12Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for digital_recognition
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆46Updated 4 years ago
- Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It …☆24Updated 4 years ago
- fpga跑sobel识别算法☆26Updated 3 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆10Updated last year
- 3×3脉动阵列乘法器☆36Updated 5 years ago
- SpinalHDL AdderNet MNIST☆9Updated 3 years ago
- to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…☆70Updated 3 years ago
- Some useful documents of Synopsys☆49Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆23Updated 5 years ago
- Integration of SIFT and LES Algorithms☆11Updated 6 months ago
- SPI interface connect to APB BUS with Verilog HDL☆25Updated 3 years ago
- 2018第二届全国大学生FPGA创新设计邀请赛的作品☆57Updated 5 years ago
- 2023集创赛国二,紫光同创杯。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆121Updated 2 weeks ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆20Updated 5 years ago
- FPGA实现动态图像识别☆13Updated 4 years ago
- ☆18Updated 2 years ago
- FPGA实现简单的图像处理算法☆40Updated last year
- Step by step tutorial for building CortexM0 SoC☆35Updated 2 years ago
- 数字IC验证案例(SV and UVM)☆25Updated 3 years ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆30Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆44Updated last year
- CNN accelerator implemented with Spinal HDL☆17Updated 2 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- fpga读取摄像头数据上传到上位机,720P@60Hz☆18Updated 3 years ago
- 帧差法运动目标检测,基于ZYNQ7020☆50Updated 3 years ago
- Pynq computer vision examples with an OV5640 camera☆46Updated 4 years ago
- upgrade to e203 (a risc-v core)☆37Updated 4 years ago
- 使用FPGA实现CNN模型☆13Updated 5 years ago
- IC Verification & SV Demo☆45Updated 3 years ago