jefferie / digital_recognition
利用ov5640摄像头采集图像,利用4.3寸RGB屏显示捕获到的数字,并将识别到的数字显示在数码管上。
☆14Updated 5 years ago
Alternatives and similar repositories for digital_recognition
Users that are interested in digital_recognition are comparing it to the libraries listed below
Sorting:
- SPI interface connect to APB BUS with Verilog HDL☆31Updated 3 years ago
- IC Verification & SV Demo☆54Updated 3 years ago
- fpga跑sobel识别算法☆34Updated 4 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆104Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆40Updated 3 years ago
- Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It …☆27Updated 4 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆174Updated 6 months ago
- Integration of SIFT and LES Algorithms☆12Updated last year
- FPGA实现动态图像识别☆21Updated 4 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆95Updated last year
- An LeNet RTL implement onto FPGA☆46Updated 7 years ago
- 2018第二届全国大学生FPGA创新设计邀请赛的作品☆59Updated 6 years ago
- Convolutional Neural Network RTL-level Design☆51Updated 3 years ago
- AXI总线连接器☆97Updated 5 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆31Updated 4 years ago
- AXI Interconnect☆47Updated 3 years ago
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆40Updated 4 years ago
- 3×3脉动阵列乘法器☆44Updated 5 years ago
- CNN accelerator implemented with Spinal HDL☆17Updated 3 years ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆45Updated 2 months ago
- This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.☆13Updated 3 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆48Updated 5 years ago
- 使用FPGA实现CNN模型☆14Updated 5 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆148Updated 2 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- 数字IC秋招项目、手撕代码☆35Updated last year
- ☆52Updated 2 years ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆26Updated 2 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆63Updated 8 months ago