The Dark Channel Prior technique is implemented on FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.
☆66Jun 11, 2024Updated 2 years ago
Alternatives and similar repositories for Hardware-Implementation-of-the-Dark-Channel-Prior-Haze-Removal-Algorithm
Users that are interested in Hardware-Implementation-of-the-Dark-Channel-Prior-Haze-Removal-Algorithm are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Constrast limited adaptive histogram equlization based on Verilog☆41Jul 21, 2023Updated 3 years ago
- Hardware Architecture for 30fps Full-HD Guided Image Filter☆12Jul 20, 2019Updated 7 years ago
- The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient t…☆52Apr 22, 2024Updated 2 years ago
- ☆24Mar 25, 2023Updated 3 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆13Jul 14, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This open-source repository aims to stitch several separate video streams into a single video using DDR3/4 storage via the AXI interface.…☆22Oct 28, 2024Updated last year
- Verilog Implementation of Otsu's algorithm☆14Jan 18, 2020Updated 6 years ago
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛(高云赛道)项目,题目基于高云FPGA的多路网络视频监控编码系统。☆71Dec 11, 2023Updated 2 years ago
- 基于FPGA进行车牌识别☆126Oct 19, 2023Updated 3 years ago
- verilog实现CLAHE(限制对比度自适应直方图均衡化)算法,并进行资源优化,含vivado综合工程。 // Verilog implementation of CLAHE (Contrast Limited Adaptive Histogram…☆21Apr 30, 2026Updated 5 months ago
- 2024嵌赛FPGA紫光同创赛题三——PixelFuze☆14May 19, 2026Updated 5 months ago
- 2024年全国大学生嵌入式芯片与系统设计竞赛 FPGA创新设计赛道 国一+易灵思创新杯获奖作品 Ultra-Vision (基于Ti60F225的无极缩放算法实现)☆117Aug 29, 2026Updated last month
- Zynq/FPGA实现CNN手写数字(0-9)识别☆45Dec 14, 2024Updated last year
- video stream scaler based on FPGA and verilog☆20Mar 28, 2024Updated 2 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- FPGA图像处理仿真平台☆31Apr 25, 2022Updated 4 years ago
- 【例程】简单的FPGA入门项目 适用于各类Cyclone 开发板☆37Dec 4, 2025Updated 10 months ago
- Quickly update a bitstream with new RAM contents☆17Jun 8, 2021Updated 5 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆53Apr 23, 2020Updated 6 years ago
- Implementation of Canny Edge Detection on Cyclone IV. To run project you need Quartus and ModelSim.☆15Mar 29, 2020Updated 6 years ago
- 基于verilog实现了ISP图像处理IP(Altera EP4CE6)☆25Jul 15, 2022Updated 4 years ago
- A novel architectural design for stitching video streams in real-time on an FPGA.☆134Oct 25, 2021Updated 4 years ago
- Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA☆44Nov 8, 2021Updated 4 years ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆49Nov 27, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Bitmap Processing Library & AXI-Stream Video Image VIP☆37Apr 11, 2022Updated 4 years ago
- 🕘 武汉理工大学中国语文网站刷时长工具(Flutter-Desktop)☆13Mar 24, 2022Updated 4 years ago
- 机器人使用了Xilinx的SPARTAN-6系列芯片以及ISE设计工具对机器人控制电路进行了设计和仿真,验证了电路的正确性和可靠性。同时机器人使用了温湿度传感器、人体感应传感器、超声波传感器、震动传感器、有毒气体传感器等,可以对灾区的环境和受困人员进行多方面的检测和响应。还…☆12Nov 15, 2023Updated 2 years ago
- We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.☆32May 18, 2019Updated 7 years ago
- 一个基于AXI接口的PL端卷积加速器,可由PS端调用☆12Apr 15, 2023Updated 3 years ago
- 代码在这个库里 Code is here☆66Oct 2, 2026Updated 3 weeks ago
- This repository is used to store RTL code for combining a single video source from multiple video sources.☆20Oct 28, 2024Updated last year
- OscillatorIMP ecosystem FPGA IP sources☆28Feb 22, 2026Updated 8 months ago
- A Convolutional Neural Network Accelerator implementation on FPGA, xilinx (xczu7ev-ffvc1156-2-i), The inference of yolov8 took 60ms.☆582Jul 17, 2025Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- MIPI CSI-2 Camera Sensor Receiver V2 Verilog HDL implementation For any generic FPGA. Tested with IMX219 IMX477 on Lattice Crosslink NX w…☆70Feb 13, 2025Updated last year
- An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。☆41Sep 18, 2024Updated 2 years ago
- 视频旋转(2019FPGA大赛)☆42May 5, 2020Updated 6 years ago
- ☆14Nov 7, 2021Updated 4 years ago
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车,分为两个部分,控制器部分和小车部分,通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势,从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆15Mar 10, 2019Updated 7 years ago
- Verilog based FPGA Design of SHA256 Simulated on ModelSim☆24May 18, 2018Updated 8 years ago
- implementation in verilog rtl for an FPGA to detect the presence of a face in an image☆13Mar 12, 2021Updated 5 years ago