The Dark Channel Prior technique is implemented on FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.
☆59Jun 11, 2024Updated last year
Alternatives and similar repositories for Hardware-Implementation-of-the-Dark-Channel-Prior-Haze-Removal-Algorithm
Users that are interested in Hardware-Implementation-of-the-Dark-Channel-Prior-Haze-Removal-Algorithm are comparing it to the libraries listed below
Sorting:
- Constrast limited adaptive histogram equlization based on Verilog☆40Jul 21, 2023Updated 2 years ago
- The Final Project of team 8, NTUEE, Digital Circuits Lab (2021 Fall)☆37Feb 26, 2022Updated 4 years ago
- 2024嵌赛FPGA紫光同创赛题三——PixelFuze☆12Nov 10, 2024Updated last year
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛（高云赛道）项目，题目基于高云FPGA的多路网络视频监控编码系统。☆62Dec 11, 2023Updated 2 years ago
- 基于FPGA进行车牌识别☆96Oct 19, 2023Updated 2 years ago
- 2024年全国大学生嵌入式芯片与系统设计竞赛 FPGA创新设计赛道 国一+易灵思创新杯获奖作品 Ultra-Vision （基于Ti60F225的无极缩放算法 实现）☆85Mar 19, 2025Updated 11 months ago
- Zynq/FPGA实现CNN手写数字(0-9)识别☆38Dec 14, 2024Updated last year
- The MEISHA V100 contains four 64-bit RISC-V RV64GC，a 5-stage in-order scalar pipeline, comprehensive peripherals and interfaces. The syst…☆18Feb 2, 2026Updated last month
- FPGA图像处理仿真平台☆28Apr 25, 2022Updated 3 years ago
- An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。☆39Sep 18, 2024Updated last year
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆51Jul 31, 2024Updated last year
- Bitmap Processing Library & AXI-Stream Video Image VIP☆35Apr 11, 2022Updated 3 years ago
- 基于verilog实现了ISP图像处理IP☆322Nov 28, 2022Updated 3 years ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆39Nov 27, 2022Updated 3 years ago
- An FPGA-based NFC (RFID) reader with a simple circuit rather than RFID chips. 用FPGA+分立器件电路搭建一个NFC(RFID)读卡器，不需要专门的RFID芯片。☆144Jan 26, 2024Updated 2 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- fpga跑sobel识别算法☆44Mar 15, 2021Updated 5 years ago
- MD5 core in verilog☆13May 1, 2012Updated 13 years ago
- Master Thesis☆10Jan 28, 2023Updated 3 years ago
- Build a Kubernetes (K8s) cluster and configure the OAI 5G core network and UERANSIM GNB + UEs on it☆10Nov 10, 2025Updated 4 months ago
- RADIX-4 SRT division☆12Oct 31, 2019Updated 6 years ago
- This repository is used to store RTL code for combining a single video source from multiple video sources.☆18Oct 28, 2024Updated last year
- Public repository for the Colosseum Young Gladiators Workshop School of 2023☆11Jun 6, 2023Updated 2 years ago
- Applying various image enhancement algorithms on Night Vision IR images using Xilinx Vivado☆15Oct 27, 2023Updated 2 years ago
- ☆12May 27, 2024Updated last year
- AI 应用服务平台☆32Nov 12, 2025Updated 4 months ago
- ☆10Jun 27, 2025Updated 8 months ago
- ISP☆13Nov 25, 2023Updated 2 years ago
- 仅注册一个邮箱，实现Cursor无限账号注册☆14Jul 2, 2025Updated 8 months ago
- Allows to reproduce the figures and the appendix of the paper "Correctly Modeling TX and RX Chain in (Distributed) Massive MIMO - New Fun…☆13Jun 30, 2022Updated 3 years ago
- Open5GS 5GC & UERANSIM UE / RAN Sample Configuration - Select UPF based on S-NSSAI☆13Apr 1, 2024Updated last year
- All You Need to Know About QDMA☆17Jun 30, 2023Updated 2 years ago
- 一个基于AXI接口的PL端卷积加速器，可由PS端调用☆13Apr 15, 2023Updated 2 years ago
- Python Wireless Channel Simulator☆11Sep 19, 2024Updated last year
- ☆13Sep 24, 2023Updated 2 years ago
- 108下 計算機組織 Computer Organization 李毅郎☆11Feb 22, 2021Updated 5 years ago
- A deep learning CNN model to predict diseases in plants using the famous AlexNet architecture☆12May 12, 2021Updated 4 years ago
- 中南大学FYT战队24赛季国赛雷达☆13Aug 15, 2024Updated last year
- Code for a model-based version of Constrained Policy Optimization☆11May 6, 2021Updated 4 years ago