Baungarten-CINVESTAV / AI_by_AILinks
AI by AI
☆11Updated last year
Alternatives and similar repositories for AI_by_AI
Users that are interested in AI_by_AI are comparing it to the libraries listed below
Sorting:
- Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.☆270Updated 6 months ago
- Communication framework for RTL simulation and emulation.☆301Updated this week
- https://caravel-user-project.readthedocs.io☆220Updated 7 months ago
- Universal Memory Interface (UMI)☆153Updated this week
- Virtual Machine for analog with the open source Sky130A PDK☆50Updated 2 months ago
- Verilog package manager written in Rust☆143Updated last year
- Demo: how to create a custom EBRICK☆23Updated 10 months ago
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆158Updated last year
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆353Updated 7 months ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆420Updated this week
- ☆117Updated 2 years ago
- ☆350Updated 2 years ago
- Repository of files associated with the webinar on analog layout using magic and klayout with Matt Venn.☆14Updated 2 years ago
- Dockerized FPGA toolchains containing openxc7, f4pga, vivado and more☆14Updated 6 months ago
- Solving Sudokus using open source formal verification tools☆18Updated 3 years ago
- ☆47Updated 2 years ago
- RISC-V CPU for OpenFPGAs, in Icestudio☆94Updated last year
- Index of the fully open source process design kits (PDKs) maintained by Google.☆104Updated 3 years ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆253Updated 3 years ago
- ☆171Updated 2 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆186Updated last week
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆48Updated last week
- Run 64-bit Linux on LiteX + RocketChip☆202Updated 2 months ago
- Simple 8-bit UART realization on Verilog HDL.☆110Updated last year
- VeeR EL2 Core☆297Updated this week
- Open-source IPs Package Manager (IPM)☆15Updated 7 months ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆96Updated 3 months ago
- Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs☆73Updated 2 months ago
- 10Gb Ethernet Switch☆232Updated last week