Alternatives and similar repositories for talk-simd-llvm:

Users that are interested in talk-simd-llvm are comparing it to the libraries listed below

• CircuitCoder / ld.meow.so
  Toy ELF dynlinker & interp
  ☆10Updated 7 months ago
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆18Updated this week
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated 10 months ago
• cnrv / OSEDA
  Open-Source EDA workshop for RISC-V community
  ☆12Updated 2 years ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• CircuitCoder / MeoWave
  ☆10Updated last year
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆16Updated 2 months ago
• chipsalliance / chisel-nix
  Nix template for the chisel-based industrial designing flows.
  ☆34Updated this week
• jiegec / kb
  My knowledge base
  ☆42Updated this week
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆21Updated last year
• loongarch64-archive / grub
  GNU GRUB https://git.savannah.gnu.org/git/grub.git
  ☆16Updated last year
• comparch-security / FlexiCAS
  A Flexible Cache Architectural Simulator
  ☆13Updated last month
• plctlab / riscv-cluster
  Towards a million-node RISC-V cluster.
  ☆13Updated 2 years ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 3 years ago
• xen0n / larva
  PoC LoongArch - RISC-V emulator
  ☆30Updated last year
• loongson / binutils-gdb
  Unofficial mirror of sourceware binutils-gdb repository. Updated daily.
  ☆10Updated last year
• n-eiling / cuda-fatbin-decompression
  ☆12Updated last year
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆44Updated this week
• CircuitCoder / cidr-calc
  CIDR union / subtraction
  ☆14Updated last week
• jiegec / unofficial-loongarch-intrinsics-guide
  Unofficial LoongArch Intrinsics Guide
  ☆41Updated last week
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆18Updated this week
• JohndeVostok / APE
  A GPU FP32 computation method with Tensor Cores.
  ☆19Updated 2 years ago
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 2 years ago
• ziyao233 / barv
  RISC-V VM in Bash
  ☆24Updated 9 months ago
• sequencer / zaozi
  The experimental work to rewrite Chisel in pure Scala 3 and the Panama Project
  ☆20Updated this week
• AOSC-Dev / chromium-loongarch64
  Maintain patches for running chromium on loongarch64
  ☆12Updated 2 weeks ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆26Updated last week
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆18Updated 3 weeks ago