Alternatives and similar repositories for riscv-cluster

Users that are interested in riscv-cluster are comparing it to the libraries listed below

• ISRC-CAS / tarsier-oerv
  Project magament for porting openEuler to RISC-V
  ☆34Updated 2 years ago
• jiegec / kb
  My knowledge base
  ☆76Updated last week
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 3 years ago
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 3 years ago
• xen0n / larva
  PoC LoongArch - RISC-V emulator
  ☆32Updated 2 years ago
• rustsbi / rustsbi-hifive-unmatched
  RustSBI support on SiFive FU740 board; FU740 is a five-core heterogeneous processor with four SiFive U74 cores, and one SiFive S7 core
  ☆17Updated 2 years ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 4 years ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 3 years ago
• cnrv / OSEDA
  Open-Source EDA workshop for RISC-V community
  ☆12Updated 3 years ago
• jiegec / apple-pmu
  Dump Apple PMU counter definitions from `/usr/share/kpep` in macOS
  ☆16Updated last week
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• JohndeVostok / APE
  A GPU FP32 computation method with Tensor Cores.
  ☆26Updated last month
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆14Updated 3 years ago
• oscomp / proj6-user-level-interrupt
  基于FPGA实现用户态中断硬件机制与优化操作系统内核
  ☆10Updated 9 months ago
• CircuitCoder / mill
  RV32I by cats
  ☆15Updated 2 years ago
• thu-cs-lab / tanlabs
  Tsinghua Advanced Networking Labs on FPGA
  ☆39Updated last year
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆46Updated last week
• NickCao / cumu
  ☆11Updated 2 years ago
• jiegec / verilog-format
  A naive verilog/systemverilog formatter
  ☆21Updated 9 months ago
• jiegec / SPECCPU2017Harmony
  Run SPEC CPU 2017 benchmark on OpenHarmony/HarmonyOS NEXT
  ☆32Updated 6 months ago
• IPADS-DuVisor / kvm-tutorial
  ☆23Updated 2 years ago
• jiegec / unofficial-loongarch-intrinsics-guide
  Unofficial LoongArch Intrinsics Guide
  ☆66Updated 3 weeks ago
• dramforever / opensbi-h
  [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆42Updated 5 months ago
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆20Updated last year
• oscomp / proj23-lightweight-hypervisor
  在RISC-V处理器上实现一个轻量级的Hypervisor。
  ☆12Updated 5 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 2 months ago
• efeslab / eecs582
  Course website for Advanced Operating Systems
  ☆13Updated 3 years ago