CircuitCoder / MeoWave
☆10Updated last year
Alternatives and similar repositories for MeoWave:
Users that are interested in MeoWave are comparing it to the libraries listed below
- Toy ELF dynlinker & interp☆10Updated 10 months ago
- CIDR union / subtraction☆14Updated 2 months ago
- Run SPEC CPU 2017 benchmark on OpenHarmony/HarmonyOS NEXT☆12Updated 2 months ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Updated 3 years ago
- RISC-V VM in Bash☆24Updated last week
- User-mode trap-and-emulate hypervisor for RISC-V☆13Updated 3 years ago
- A hand-written recursive decent Verilog parser.☆11Updated 2 years ago
- A 3d printed case design for Lichee Pi 4A☆12Updated last year
- ☆11Updated 11 months ago
- A hardware accelerated IP packet forwarder running on programmable ICs☆16Updated 2 years ago
- RV32I by cats☆17Updated last year
- WIP: A fork of OpenSBI, with software-emulated hypervisor extension support☆38Updated last month
- Relaxed Rust (for cats)☆16Updated 5 years ago
- What if everything is a io_uring?☆16Updated 2 years ago
- Convert shared libraries into relocatable objects☆10Updated last year
- A Rust style C++ library.☆19Updated 2 years ago
- ☆17Updated 3 years ago
- Follow nginx log, and find out bad guys!☆19Updated 2 weeks ago
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- Compile Time RapidJSON: A compile time C++ header only JSON library without bloating yet another hand-crafted JSON parser based on RapidJ…☆15Updated 4 years ago
- Open-source RISC-V cryptographic hardware token, RTL repo☆19Updated 2 years ago
- 红人的女装☆8Updated 3 years ago
- Header-only C/C++ static keys to avoid the overhead of conditional branches☆13Updated last year
- Nix template for the chisel-based industrial designing flows.☆41Updated this week
- PKU CompNet'19 Lab 2 - Homebrew TCP☆12Updated 5 years ago
- PoC LoongArch - RISC-V emulator☆32Updated last year
- A naive verilog/systemverilog formatter☆20Updated 3 weeks ago
- HERMES: sHallow dirEctory stRucture Many-filE fileSystem☆20Updated 5 years ago
- A mini (consistent-wannabe) proof-assistant with power roughly equivalent to intelligence of a two month old cat☆17Updated 3 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago