hht238000 / QP_solver-LVI_PDNN-FPGA_Implementation
Design and Implementation of Primal-Dual Neural Network FPGA Based on LVI for Solving Quadratic Programming Problems
☆9Updated 4 years ago
Alternatives and similar repositories for QP_solver-LVI_PDNN-FPGA_Implementation:
Users that are interested in QP_solver-LVI_PDNN-FPGA_Implementation are comparing it to the libraries listed below
- ☆69Updated 4 years ago
- This repository contains code and pdf tutorial of how I've implemented binocular camera matching algorithm, SGBM, with FPGA using verilog…☆32Updated 2 years ago
- Integration of SIFT and LES Algorithms☆12Updated 10 months ago
- Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Veril…☆22Updated 2 years ago
- KR260 Ubuntu 22.04 firmware. Package for enabling hardware acceleration capabilities in ROS 2 Humble with KR260 and Ubuntu 22.04.☆10Updated 2 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆92Updated last year
- Real-time binocular stereo vision FPGA system with OV5640 cameras☆68Updated 2 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆49Updated 7 years ago
- ☆35Updated last year
- 利用ov5640摄像头采集图像,利用4.3寸RGB屏显示捕获到的数字,并将识别到的数字显示在数码管上。☆12Updated 4 years ago
- FPGA Hardware Implementation for SLAM☆67Updated 4 months ago
- Zedboard projects☆10Updated 8 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆70Updated last year
- 2019 SEU-Xilinx Summer School☆48Updated 5 years ago
- Real-time binocular stereo vision FPGA system with OV5640 cameras☆28Updated 5 years ago
- Vitis Model Composer Examples and Tutorials☆94Updated this week
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 4 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆10Updated 9 months ago
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆36Updated 4 years ago
- Hardware-Efficient Stereo Vision for Embedded Applications on FPGAs☆36Updated 4 years ago
- Deployment of Deep learning Image Super-Resolution Models in Xilinx Zynq MPSoC ZCU102☆16Updated 4 years ago
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…☆15Updated 3 years ago
- 使用FPGA实现CNN模型☆13Updated 5 years ago
- This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.☆14Updated 3 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- 七路图像在FPGA中实现拼接,代码会不断添加进来。☆24Updated 3 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆28Updated 4 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Updated 9 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago