Alternatives and similar repositories for HW-Formal-Paper:

Users that are interested in HW-Formal-Paper are comparing it to the libraries listed below

• gipsyh / rIC3
  Hardware Model Checker
  ☆40Updated this week
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆40Updated 3 months ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆64Updated 4 years ago
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆14Updated 6 years ago
• aman-goel / avr
  Reads a state transition system and performs property checking
  ☆77Updated 3 weeks ago
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 5 years ago
• Moorvan / ChiselFV
  A Formal Verification Framework for Chisel
  ☆18Updated 11 months ago
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆9Updated 5 months ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆65Updated this week
• gipsyh / rIC3-HWMCC24
  rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission
  ☆11Updated 6 months ago
• Moorvan / RISCV-Formal-Chisel
  RISC-V Formal in Chisel
  ☆11Updated 11 months ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆22Updated 4 years ago
• ekiwi / simulator-independent-coverage
  Project Repo for the Simulator Independent Coverage Research
  ☆18Updated 2 years ago
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆69Updated 2 weeks ago
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆57Updated last week
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆75Updated 8 months ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆12Updated 9 months ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆22Updated 4 years ago
• hackdac / hackdac_2018_beta
  The SoC used for the beta phase of Hack@DAC 2018.
  ☆17Updated 4 years ago
• stanford-centaur / pono
  Pono: A flexible and extensible SMT-based model checker
  ☆94Updated this week
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆20Updated 2 months ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆32Updated 3 years ago
• iscas-tis / CHA
  ☆17Updated 8 months ago
• iscas-tis / riscv-spec-core
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆12Updated last week
• efeslab / asplos22-hardware-debugging-artifact
  ☆11Updated 9 months ago
• shaowei-cai-group / X-SAT
  An advanced circuit-based sat solver
  ☆17Updated last month
• efeslab / hardware-bugbase
  ☆17Updated 9 months ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆28Updated 8 months ago
• hammad-a / verilog_repair
  Automated Repair of Verilog Hardware Descriptions
  ☆27Updated 2 months ago
• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago