benpye / nix-fpga-toolsLinks
☆26Updated 3 years ago
Alternatives and similar repositories for nix-fpga-tools
Users that are interested in nix-fpga-tools are comparing it to the libraries listed below
Sorting:
- HDL development environment on Nix.☆26Updated 11 months ago
- Haskell library for hardware description☆104Updated 2 months ago
- 32-bit RISC-V Emulator☆26Updated 6 years ago
- ☆30Updated 4 years ago
- NixOS on Allwinner D1 RISC-V☆39Updated 3 years ago
- Playground for experimenting with and sharing short Amaranth programs on the web☆16Updated last week
- CPOL=0, CPHA=0 SPI core for practicing formal verification with yosys☆21Updated 5 years ago
- Yosys plugin for synthesis of Bluespec code☆15Updated 4 years ago
- Generate interface between Clash and Verilator☆22Updated last year
- NixOS on Xilinx Zynq and ZynqMP☆39Updated 2 weeks ago
- A Verilog parser for Haskell.☆36Updated 4 years ago
- ☆14Updated last year
- An FPGA reverse engineering and documentation project☆58Updated this week
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- Nix Expressions for Altera(Intel) Quartus☆16Updated 4 years ago
- End-to-end synthesis and P&R toolchain☆89Updated last month
- Industry standard I/O for Amaranth HDL☆29Updated last year
- Whisk: 16-bit serial processor for TT02☆13Updated last year
- Deploying Haskell to Lattice iCE40 using fully open source toolchain☆13Updated 9 years ago
- Hot Reconfiguration Technology demo☆40Updated 3 years ago
- Experiments with Yosys cxxrtl backend☆50Updated 9 months ago
- ☆22Updated last week
- Projects to get started with Clash☆30Updated last month
- Manythread RISC-V overlay for FPGA clusters☆38Updated last month
- Fiber-based SystemVerilog Simulator.☆25Updated 3 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆29Updated last week
- RFCs for changes to the Amaranth language and standard components☆18Updated this week
- NixOS on the HiFive Unmatched☆99Updated 2 years ago
- A 16-bit CPU and self-hosting Forth system for the Lattice ICE40 FPGA, written in Haskell.☆59Updated 4 years ago
- Kansas Lava☆49Updated 6 years ago