pemb / siphashLinks
A VHDL implementation of SipHash
☆13Updated 10 years ago
Alternatives and similar repositories for siphash
Users that are interested in siphash are comparing it to the libraries listed below
Sorting:
- Security monitor for Keystone Enclave (mirror of riscv-pk). Will be deprecated when openSBI port is ready☆35Updated 4 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆55Updated 6 years ago
- Framework for building transparent memory encryption and authentication solutions☆27Updated 7 years ago
- Multiplication using AVX512 and AVX512IFMA instructions☆23Updated 10 years ago
- FLECC_IN_C is a FLexible Elliptic Curve Cryptography library written IN C☆18Updated 8 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆41Updated 9 years ago
- XCrypto: a cryptographic ISE for RISC-V☆92Updated 2 years ago
- Hardware implementation of the blake2 hash function☆25Updated 5 years ago
- Hardware implementation of the SipHash short-inout PRF☆17Updated 7 months ago
- Oblivious Memory Access under Fully Homomorphic Encryption☆13Updated 10 years ago
- Snowshoe - Portable, Secure, Fast Elliptic Curve Math Library in C☆63Updated 7 years ago
- Finalists to the NIST lightweight cryptography competition☆38Updated 3 years ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆36Updated 4 years ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- The Antikernel operating system project☆119Updated 5 years ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- A (Py)thon (D)SL for (G)enerating (In)struction set simulators.☆167Updated 7 years ago
- SDK for Keystone Enclave - ABI/SBI libraries and sample apps☆44Updated 3 years ago
- Authenticated Encryption Based on the Masked Even-Mansour (MEM) Construction☆28Updated 7 years ago
- Implementations of the Simon and Speck Block Ciphers☆101Updated 7 years ago
- A 300 MHz to 3800 MHz RF module for the Novena Open Hardware Computing Platform☆53Updated 9 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 5 years ago
- An online Verilog IDE based on YosysJS.☆24Updated 9 years ago
- A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.☆36Updated 3 years ago
- Verilog 2001 implementation of the ChaCha stream cipher.☆44Updated 7 months ago
- ☆19Updated 10 years ago
- An open standard Cache Coherent Fabric Interface repository☆66Updated 5 years ago
- Software, tools, documentation for Vegaboard platform☆64Updated 6 years ago
- A 32-bit RISC-V processor for mriscv project☆59Updated 8 years ago
- A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure☆16Updated 6 years ago