Alternatives and similar repositories for siphash

Users that are interested in siphash are comparing it to the libraries listed below

• keystone-enclave / riscv-pk
  Security monitor for Keystone Enclave (mirror of riscv-pk). Will be deprecated when openSBI port is ready
  ☆35Updated 4 years ago
• scarv / xcrypto
  XCrypto: a cryptographic ISE for RISC-V
  ☆92Updated 2 years ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆55Updated 6 years ago
• isec-tugraz / flecc_in_c
  FLECC_IN_C is a FLexible Elliptic Curve Cryptography library written IN C
  ☆18Updated 8 years ago
• Poofjunior / fpga_fast_serial_sort
  a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  ☆41Updated 9 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆42Updated 6 years ago
• secworks / chacha
  Verilog 2001 implementation of the ChaCha stream cipher.
  ☆44Updated 8 months ago
• secworks / siphash
  Hardware implementation of the SipHash short-inout PRF
  ☆17Updated 8 months ago
• onchipuis / mriscvcore
  A 32-bit RISC-V processor for mriscv project
  ☆59Updated 8 years ago
• secworks / blake2
  Hardware implementation of the blake2 hash function
  ☆25Updated 5 years ago
• isec-tugraz / memsec
  Framework for building transparent memory encryption and authentication solutions
  ☆27Updated 7 years ago
• cornell-brg / pydgin
  A (Py)thon (D)SL for (G)enerating (In)struction set simulators.
  ☆167Updated 7 years ago
• jameshegarty / rigel
  Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…
  ☆56Updated 5 years ago
• ZipCPU / zipversa
  A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure
  ☆17Updated 6 years ago
• azonenberg / antikernel
  The Antikernel operating system project
  ☆119Updated 5 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆50Updated 8 years ago
• admk / soap
  soap - Structural Optimisation of Arithmetic Programs
  ☆24Updated 9 years ago
• inmcm / Simon_Speck_Ciphers
  Implementations of the Simon and Speck Block Ciphers
  ☆101Updated 7 years ago
• cseed / cynth
  a simple C-to-Verilog compiler
  ☆51Updated 8 years ago
• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆36Updated 4 years ago
• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆64Updated 6 years ago
• vkrasnov / vpmadd
  Multiplication using AVX512 and AVX512IFMA instructions
  ☆23Updated 10 years ago
• JohnDRO / Golirev-IDE
  An online Verilog IDE based on YosysJS.
  ☆24Updated 9 years ago
• chipy-hdl / chipy
  chipy hdl
  ☆17Updated 7 years ago
• parallella / parallella-riscv
  RISC-V port to Parallella Board
  ☆13Updated 9 years ago
• ReconOS / reconos
  ReconOS - Operating System for Reconfigurable Hardware
  ☆29Updated 3 years ago
• mmattioli / aes
  AES-128 hardware implementation
  ☆33Updated 5 years ago
• daniellustig / pipecheck
  ☆19Updated 10 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• warclab / dyract
  DyRACT Open Source Repository
  ☆16Updated 9 years ago