Alternatives and similar repositories for siphash

Users that are interested in siphash are comparing it to the libraries listed below

• keystone-enclave / riscv-pk
  Security monitor for Keystone Enclave (mirror of riscv-pk). Will be deprecated when openSBI port is ready
  ☆35Updated 4 years ago
• secworks / blake2
  Hardware implementation of the blake2 hash function
  ☆25Updated 4 years ago
• secworks / siphash
  Hardware implementation of the SipHash short-inout PRF
  ☆17Updated 3 months ago
• secworks / chacha
  Verilog 2001 implementation of the ChaCha stream cipher.
  ☆40Updated 3 months ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆56Updated 5 years ago
• Poofjunior / fpga_fast_serial_sort
  a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  ☆40Updated 9 years ago
• vkrasnov / vpmadd
  Multiplication using AVX512 and AVX512IFMA instructions
  ☆23Updated 9 years ago
• onchipuis / mriscvcore
  A 32-bit RISC-V processor for mriscv project
  ☆58Updated 8 years ago
• keystone-enclave / keystone-sdk
  SDK for Keystone Enclave - ABI/SBI libraries and sample apps
  ☆44Updated 2 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆42Updated 6 years ago
• catid / snowshoe
  Snowshoe - Portable, Secure, Fast Elliptic Curve Math Library in C
  ☆63Updated 7 years ago
• isec-tugraz / flecc_in_c
  FLECC_IN_C is a FLexible Elliptic Curve Cryptography library written IN C
  ☆18Updated 7 years ago
• scarv / xcrypto
  XCrypto: a cryptographic ISE for RISC-V
  ☆93Updated 2 years ago
• isec-tugraz / memsec
  Framework for building transparent memory encryption and authentication solutions
  ☆27Updated 7 years ago
• cliffordwolf / xbitmanip
  RISC-V XBitmanip Extension
  ☆26Updated 6 years ago
• regehr / const_time
  empirical measurement of code constructs that seem like they should have constant execution time regardless of values of inputs
  ☆8Updated 9 years ago
• betrusted-io / gateware
  IP submodules, formatted for easier CI integration
  ☆30Updated last year
• JohnDRO / Golirev-IDE
  An online Verilog IDE based on YosysJS.
  ☆24Updated 9 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆49Updated 8 years ago
• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆63Updated 6 years ago
• chipy-hdl / chipy
  chipy hdl
  ☆17Updated 7 years ago
• theopolis / u-boot-sboot
  U-Boot with Atmel's I2C TPM, libTLCL, and libsboot (Secure Boot)
  ☆18Updated 10 years ago
• hcrypt-project / oblivious
  Oblivious Memory Access under Fully Homomorphic Encryption
  ☆13Updated 9 years ago
• cornell-brg / pydgin
  A (Py)thon (D)SL for (G)enerating (In)struction set simulators.
  ☆166Updated 7 years ago
• keystone-enclave / keystone-runtime
  Eyrie enclave runtime kernel
  ☆36Updated last year
• jameshegarty / rigel
  Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…
  ☆56Updated 4 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆43Updated 2 years ago
• ucb-bar / fpga-spartan6
  Support for zScale on Spartan6 FPGAs
  ☆16Updated 9 years ago
• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆36Updated 4 years ago
• coruus / ed448-goldilocks
  Mirror of http://sourceforge.net/p/ed448goldilocks/code/ci/master/tree/
  ☆33Updated 10 years ago