A VHDL implementation of SipHash
☆13Feb 19, 2015Updated 11 years ago
Alternatives and similar repositories for siphash
Users that are interested in siphash are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Hardware implementation of the SipHash short-inout PRF☆18Apr 3, 2025Updated last year
- SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).☆12Oct 14, 2017Updated 8 years ago
- A clean & simple implementation of BLAKE2b and BLAKE2s hash functions -- written while writing the RFC.☆21Nov 3, 2015Updated 10 years ago
- Simple tool to regularly pool Tor HSDirs for hidden service descriptors☆10Jul 3, 2015Updated 11 years ago
- Hardware-accelerated sorting algorithm☆16May 4, 2020Updated 6 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆17Sep 4, 2014Updated 11 years ago
- an authenticated, chunked cipher based on BLAKE3☆23Jun 21, 2026Updated last month
- Gentoo overlay for Tox clients and Tox related projects☆20May 23, 2016Updated 10 years ago
- Open SoC Debug Hardware Reference Implementation☆16Jul 15, 2019Updated 7 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 9 years ago
- Description of a RISC-V architecture based on MIPS 3000☆14Apr 24, 2023Updated 3 years ago
- GIAnT, the Generic Implementation ANalysis Toolkit☆12Jul 4, 2018Updated 8 years ago
- C implementation of the BlaBla20 cipher☆10Jan 1, 2026Updated 6 months ago
- ☆15Nov 28, 2016Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆14Jun 19, 2026Updated last month
- kexec-tools with hardboot support for MultiROM☆21Jul 15, 2024Updated 2 years ago
- Reference implementations of the GIMLI permutation☆15Jul 9, 2017Updated 9 years ago
- Simulates Attacks of AB16 on Argon2i☆11Aug 4, 2016Updated 9 years ago
- ☆13Aug 10, 2014Updated 11 years ago
- (Keep It) Simple Stupid Database☆10Jul 16, 2017Updated 9 years ago
- ☆17Aug 16, 2023Updated 2 years ago
- Go API client for arxiv.org☆20Feb 22, 2022Updated 4 years ago
- C library of Teserakt's E4 end-to-end security protocol☆16Feb 29, 2020Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A save editor for Monster Hunter XX for the Nintendo 3DS.☆10May 7, 2019Updated 7 years ago
- Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determine…☆15Jun 15, 2016Updated 10 years ago
- Hardware Snappy decompressor☆12Sep 11, 2024Updated last year
- FPGA video scaler running on Intel Arria 10☆12May 28, 2019Updated 7 years ago
- Bitstream Fault Analysis Tool☆16Jul 17, 2023Updated 3 years ago
- Hybrid Threading Tool Set☆15Sep 24, 2020Updated 5 years ago
- CryptonightV2 with random math proof of concept☆13Feb 26, 2019Updated 7 years ago
- Tools to convert Kicad intermediate netlist to HDL block diagram netlist☆12Jul 21, 2016Updated 10 years ago
- Powershell script to switch between logged in battlenet accounts☆10Sep 8, 2018Updated 7 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- IEEE1588v2 Precision Time Protocol implementation☆13Jun 21, 2021Updated 5 years ago
- High-througput logic analyzer for FPGA☆17Oct 8, 2020Updated 5 years ago
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 6 years ago
- This project has files needed to design and characterise flipflop☆21Jun 3, 2019Updated 7 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆13May 14, 2019Updated 7 years ago
- System-on-Chip Interconnection Network - Simulation Environment (front-end)☆16Oct 5, 2023Updated 2 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago