Alternatives and similar repositories for numfi

Users that are interested in numfi are comparing it to the libraries listed below

• francof2a / fxpmath
  A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.
  ☆202Updated last year
• ZipCPU / dblclockfft
  A configurable C++ generator of pipelined Verilog FFT cores
  ☆251Updated last year
• ZipCPU / dspfilters
  A collection of demonstration digital filters
  ☆163Updated last year
• PyFPGA / pyfpga
  A Python package to use FPGA development tools programmatically.
  ☆143Updated 9 months ago
• ggventurini / python-deltasigma
  A port of the MATLAB Delta Sigma Toolbox based on free software and very little sleep
  ☆94Updated 3 years ago
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆30Updated 11 months ago
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆57Updated 9 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆128Updated 7 months ago
• smlgit / fpbinary
  Fixed point package for Python.
  ☆36Updated 2 years ago
• raczben / zynq_flash
  QSPI flash support for Xilinx's Zynq devices
  ☆25Updated 5 years ago
• Xilinx / DSP-PYNQ
  A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+
  ☆40Updated 3 years ago
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆229Updated last week
• wallento / wavedrompy
  WaveDrom compatible python command line
  ☆112Updated 2 years ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆80Updated this week
• ZipCPU / cordic
  A series of CORDIC related projects
  ☆120Updated last year
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆81Updated 3 weeks ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆194Updated last month
• k0nze / zedboard_pl_to_ps_interrupt_example
  Tutorial on how to use the PL to PS interrupt on the Zedboard
  ☆27Updated 8 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 11 months ago
• Xilinx / PYNQ_RFSOC_Workshop
  Open-sourcing the PYNQ & RFSoC workshop materials
  ☆63Updated 5 years ago
• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆126Updated 4 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 5 months ago
• strath-sdr / rfsoc_sam
  RFSoC Spectrum Analyser Module on PYNQ.
  ☆89Updated last year
• SEL-FOSS / fixedpoint
  Fixed point arithmetic python package
  ☆38Updated 2 years ago
• strath-sdr / RFSoC-Book
  Companion Jupyter Notebooks for the RFSoC-Book.
  ☆247Updated 2 years ago
• Lenty / SLiCAP_python
  Open-source version of SLiCAP, implemented in python
  ☆37Updated last year
• rftafas / stdcores
  Standard and Curated cores, tested and working.
  ☆11Updated 3 years ago
• chipmuenk / dsp
  Unterlagen zu den Vorlesungen "Digitale Signalverarbeitung (DSV)" und "DSV auf FPGAs"
  ☆30Updated last year
• apytypes / apytypes
  APyTypes - Algorithmic data types for Python
  ☆39Updated last week
• mattvenn / fpga-sdft
  sliding DFT for FPGA, targetting Lattice ICE40 1k
  ☆76Updated 5 years ago