WenqiJiang / SC-ANN-FPGALinks
☆18Updated last week
Alternatives and similar repositories for SC-ANN-FPGA
Users that are interested in SC-ANN-FPGA are comparing it to the libraries listed below
Sorting:
- ☆66Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆18Updated last year
- Processing in Memory Emulation☆20Updated 2 years ago
- ☆24Updated 4 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆22Updated 6 years ago
- ☆26Updated 3 years ago
- ☆26Updated last year
- Public repostory for the DAC 2021 paper "Scaling up HBM Efficiency of Top-K SpMV forApproximate Embedding Similarity on FPGAs"☆14Updated 3 years ago
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆26Updated last year
- ☆28Updated 2 years ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 3 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 5 years ago
- STONNE Simulator integrated into SST Simulator☆19Updated last year
- A list of our chiplet simulaters☆32Updated 2 months ago
- EQueue Dialect☆40Updated 3 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated 11 months ago
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 2 years ago
- FRAME: Fast Roofline Analytical Modeling and Estimation☆36Updated last year
- ☆30Updated 2 months ago
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆24Updated last year
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆53Updated 2 months ago
- ☆10Updated 2 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators☆21Updated 2 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆55Updated 5 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago