Alternatives and similar repositories for zcu102-ethernet

Users that are interested in zcu102-ethernet are comparing it to the libraries listed below

• hpcn-uam / 100G-fpga-network-stack-core
  This repo contains the Limago code
  ☆86Updated last month
• Xilinx / pcie_qdma_ats_example
  ☆24Updated 4 years ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆43Updated 2 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago
• yhqiu16 / OCOWFC
  Open-Channel Open-Way Flash Controller
  ☆16Updated 3 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆75Updated 10 years ago
• shuckc / verilog-utils
  native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
  ☆44Updated 10 years ago
• Xilinx-Wiki-Projects / ZCU102-Ethernet
  Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.
  ☆67Updated 4 months ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆40Updated 4 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆29Updated 2 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆107Updated 3 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆63Updated 5 years ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆18Updated 7 years ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆67Updated last year
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆65Updated 7 months ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆49Updated 2 years ago
• fpgasystems / davos
  Distributed Accelerator OS
  ☆63Updated 3 years ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆104Updated 2 years ago
• amiq-consulting / amiq_eth
  Library defining all Ethernet packets in SystemVerilog and in SystemC
  ☆37Updated 8 years ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆38Updated last year
• yhqiu16 / NVMeCHA
  NVMe Controller featuring Hardware Acceleration
  ☆89Updated 4 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆74Updated 10 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆35Updated 4 years ago
• sach / System-Verilog-Packet-Library
  System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers
  ☆76Updated 6 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆51Updated last year
• freecores / ha1588
  Hardware Assisted IEEE 1588 IP Core
  ☆29Updated 10 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆55Updated 2 years ago
• ttchisholm / 10g-low-latency-ethernet
  10G Low Latency Ethernet
  ☆55Updated last year
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆34Updated 7 years ago