PrimeMHD / FPGA_ThreeLevelStorageLinks
【原创,已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计,FPGA三级存储子系统。
☆119Updated 5 years ago
Alternatives and similar repositories for FPGA_ThreeLevelStorage
Users that are interested in FPGA_ThreeLevelStorage are comparing it to the libraries listed below
Sorting:
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆86Updated 6 years ago
- 实现一个基础但功能完善的计算机系统,根据《自己动手写CPU》实现,开发板为Nexys4 DDR☆34Updated last year
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆147Updated last year
- Asymmetric dual issue in-order microprocessor.☆33Updated 6 years ago
- 为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助☆134Updated 5 years ago
- ☆72Updated 2 years ago
- 一生一芯的信息发布和内容网站☆136Updated 2 years ago
- A softcore microprocessor of MIPS32 architecture.☆40Updated last year
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC(精简指令集)CPU(中央处理器)简单结构和Verilog实现。☆162Updated 7 years ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆66Updated 3 years ago
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆42Updated 7 years ago
- NSCSCC 信息整合☆252Updated 4 years ago
- ☆64Updated 3 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆50Updated 2 years ago
- ☆92Updated 4 months ago
- 计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9☆34Updated 4 years ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆182Updated 4 years ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆40Updated 2 years ago
- 中国科学院大学高级计算机体系结构课程作业:使用OpenROAD-flow完成RTL到GDS全流程☆30Updated 5 years ago
- This repository is used to release the experimental assignments of Computer Architecture Course from USTC☆39Updated 6 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆61Updated 4 years ago
- Uranus MIPS processor by MaxXing & USTB NSCSCC team☆38Updated 6 years ago
- This project uses verilog to implement interaction with OV2640 camera, Bluetooth slave module and VGA display on FPGA.☆58Updated 5 years ago
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆45Updated 5 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- Naïve MIPS32 SoC implementation☆118Updated 5 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆194Updated last year
- ☆90Updated 2 months ago
- AXI协议规范中文翻译版☆171Updated 3 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆126Updated 3 years ago