Alternatives and similar repositories for clang-builtin-tutorial:

Users that are interested in clang-builtin-tutorial are comparing it to the libraries listed below

• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆114Updated 4 months ago
• NamanMakkar / ECE5545-ML-Hardware-Systems
  This repo contains the Assignments from Cornell Tech's ECE 5545 - Machine Learning Hardware and Systems offered in Spring 2023
  ☆28Updated last year
• riscv-non-isa / rvv-intrinsic-doc
  ☆322Updated 2 weeks ago
• gem5bootcamp / gem5-bootcamp-env
  The gem5 Bootcamp 2022 environment. Archived.
  ☆36Updated 9 months ago
• gem5bootcamp / 2024
  Materials, slides, and workspace for the gem5 bootcamp 2024
  ☆29Updated 8 months ago
• IAMAl / Readings-in-Computer-Architectures
  Readings in Computer Architectures
  ☆17Updated last year
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆164Updated last week
• MPSLab-ASU / ML-Accelerators
  Topics in Machine Learning Accelerator Design
  ☆72Updated 2 years ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆110Updated last month
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆50Updated 3 years ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆138Updated 2 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆82Updated 3 weeks ago
• rivosinc / veclibm
  Vector math library using RISC-V vector ISA via C intrinsic
  ☆17Updated 5 months ago
• rivosinc / gem5
  This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…
  ☆11Updated 2 years ago
• craymichael / CBP-16-Simulation
  Branch predictor simulation, analysis, and Python compatibility for the 5th Championship Branch Prediction in 2016 (CBP-16)
  ☆21Updated 2 years ago
• KULeuven-MICAS / snax-mlir
  Driving Snax with MLIR
  ☆14Updated this week
• learnwithexamples / learnsystemc
  Learn systemC with examples
  ☆109Updated 2 years ago
• pnnl / soda-opt
  ☆44Updated last month
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆67Updated this week
• ramisheikh / cbp2025
  Championship Branch Prediction 2025
  ☆40Updated 3 weeks ago
• hngenc / stellar
  ☆26Updated 5 months ago
• compiler-dev / llvm-rv
  Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension
  ☆43Updated 4 years ago
• dcblack / ModernSystemC
  Example code for Modern SystemC using Modern C++
  ☆61Updated 2 years ago
• riscvarchive / riscv-code-size-reduction
  ☆150Updated last year
• mathis-s / SoomRV
  A simple superscalar out-of-order RISC-V microprocessor
  ☆202Updated 2 months ago
• riscv-admin / integrated-matrix-extension
  Administrative repository for the Integrated Matrix Extension Task Group
  ☆21Updated 3 weeks ago
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆100Updated 6 years ago
• RoyanTuscano / -TAGE-based-Predictor-Verilog-Code
  Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud
  ☆20Updated 6 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆91Updated last year
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆58Updated 6 months ago