etri / nest-snn
NEST-SNN
☆14Updated 3 years ago
Alternatives and similar repositories for nest-snn:
Users that are interested in nest-snn are comparing it to the libraries listed below
- NEST Data☆49Updated 4 years ago
- ☆14Updated 2 years ago
- NEST Compiler☆116Updated 2 months ago
- ☆28Updated last year
- Pytorch implementation of our UniQ method, IEEE Access -- Training Multi-bit Quantized and Binarized Networks with A Learnable Symmetric …☆11Updated 4 years ago
- ☆24Updated last year
- ☆24Updated 4 months ago
- ONNX for SNN(Spiking Neural Networks)☆20Updated 4 years ago
- ☆12Updated 4 years ago
- ☆39Updated 9 months ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆28Updated 6 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆12Updated 2 years ago
- ☆27Updated 4 years ago
- This repository is a meta package to provide Samsung OneMCC (Memory Coupled Computing) infrastructure.☆27Updated last year
- An automated HDC platform☆9Updated 3 weeks ago
- Neural Network Acceleration using CPU/GPU, ASIC, FPGA☆60Updated 4 years ago
- An energy simulation framework for BPTT-based SNN inference and training.☆15Updated last year
- ☆9Updated 5 years ago
- CNN simd based accelerator using Vitis HLS☆10Updated 2 years ago
- Neural Network Acceleration such as ASIC, FPGA, GPU, and PIM☆51Updated 5 years ago
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆22Updated last year
- ☆11Updated last year
- ☆34Updated 4 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆14Updated 9 months ago
- ☆33Updated 6 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 2 years ago
- NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing☆78Updated 9 months ago
- A portable framework to map DFG (dataflow graph, representing an application) on spatial accelerators.☆36Updated 2 years ago
- Framework for radix encoded SNN on FPGA☆12Updated 3 years ago
- Repository for compilation and cycle-accurate simulator for scale-out systolic arrays☆14Updated 2 years ago