neurom-iot / onnx-snn
ONNX for SNN(Spiking Neural Networks)
☆20Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for onnx-snn
- Intelligent Component Registry web service for managing and using snn, dnn, and ml models, which is stored in onnx format.☆21Updated 2 years ago
- Leaky Integrate and Fire (LIF) model implementation for FPGA☆45Updated last year
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆30Updated 5 years ago
- NeuroSync: A Scalable and Accurate Brain Simulation System using Safe and Efficient Speculation (HPCA 2022)☆8Updated 2 years ago
- Neural Network Acceleration using CPU/GPU, ASIC, FPGA☆60Updated 4 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆25Updated 6 years ago
- An energy simulation framework for BPTT-based SNN inference and training.☆14Updated last year
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆46Updated 3 years ago
- NEST Compiler☆116Updated 4 months ago
- This repository is a meta package to provide Samsung OneMCC (Memory Coupled Computing) infrastructure.☆26Updated last year
- MINT, Multiplier-less INTeger Quantization for Energy Efficient Spiking Neural Networks, ASP-DAC 2024, Nominated for Best Paper Award☆10Updated 7 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆38Updated 6 months ago
- Neural Network Acceleration such as ASIC, FPGA, GPU, and PIM☆51Updated 4 years ago
- NEST Data☆49Updated 3 years ago
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆77Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆44Updated 2 years ago
- An extention of pytorch for low precision training / inference☆9Updated last year
- ☆17Updated 3 years ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆22Updated 5 years ago
- Framework for radix encoded SNN on FPGA☆13Updated 2 years ago
- Processing-In-Memory (PIM) Simulator☆132Updated 4 months ago
- Neuromorphic Architecture Abstraction Layer☆16Updated 2 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network☆42Updated 4 years ago
- Stochastic Computing for Deep Neural Networks☆28Updated 3 years ago
- ☆10Updated 6 years ago
- ☆32Updated 5 years ago
- ☆10Updated 5 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆12Updated 4 months ago
- Spiking Neural Network Accelerator☆12Updated 2 years ago
- ☆27Updated 4 years ago