eminfedar / fedar-e1-rv32iLinks
5-Stage Pipelined RV32I RISC-V Core design in Verilog-2005. It has 32 GPIO pins and it is FPGA synthesible.
☆23Updated 2 years ago
Alternatives and similar repositories for fedar-e1-rv32i
Users that are interested in fedar-e1-rv32i are comparing it to the libraries listed below
Sorting:
- 5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.☆209Updated 4 years ago
- Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…☆20Updated 2 years ago
- Kasırga - Gök Sayısal İşlemci Kategorisi RISC-V İşlemci Tasarımı☆17Updated 2 years ago
- KASIRGA-GUN | RV32IMCX☆11Updated last year
- RISC-V RV32IM cpu circuit in Logisim Evolution.☆26Updated 4 years ago
- Kasırga Sayısal Görüntü İşleme Kategorisi Hızlandırıcı Tasarımı☆12Updated 2 years ago
- 64-bit RISC-V processor☆16Updated 2 years ago
- Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)☆34Updated last month
- Building a busybox based RiscV 64-bit GNU/Linux system from scratch☆52Updated 6 years ago
- This course is given in ERCIYES UNIVERSITY for Spring 2022-2023 semester as a fourth grade lecture. You can find lecture notes, RISC-V as…☆15Updated 2 years ago
- KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi☆152Updated 2 years ago
- 5 Stage Pipelined RISC V Processor Design for RV32I Instruction Set☆10Updated 2 years ago
- Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C☆18Updated 2 years ago
- "Mehmet Burak Aykenar" YouTube kanalında yayınlanan VHDL ve FPGA dersleri ile ilgili kodları içermektedir.☆107Updated last year
- A Single Cycle Risc-V 32 bit CPU☆49Updated last week
- Basic RISC-V Test SoC☆140Updated 6 years ago
- SystemVerilog derslerinde yazdığım kodları içermektedir.☆14Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆104Updated last year
- PCIe GEN1, GEN2 and GEN3 Scrambler, This Scrambler is able to scramble 1,2 and 4 bytes of data in 1 clock cycle in respect to the scrambl…☆14Updated last month
- A simple RISC V core for teaching☆193Updated 3 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆133Updated 5 years ago
- ECE 3300 HDL Code☆56Updated 2 years ago
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆139Updated 3 months ago
- Verilog HDL files☆149Updated last year
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆143Updated 4 years ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆120Updated 4 years ago
- This repository contains the design files of RISC-V Pipeline Core☆51Updated 2 years ago
- Implementation of RISC-V RV32I☆21Updated 3 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆112Updated last week
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆303Updated 7 years ago