Alternatives and similar repositories for fedar-e1-rv32i:

Users that are interested in fedar-e1-rv32i are comparing it to the libraries listed below

• eminfedar / fedar-f1-rv64im
  5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.
  ☆198Updated 3 years ago
• TUTEL-TUBITAK / TEKNOFEST_2023_Cip_Tasarim_Yarismasi
  Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…
  ☆20Updated last year
• mbaykenar / computer-architecture
  This course is given in ERCIYES UNIVERSITY for Spring 2022-2023 semester as a fourth grade lecture. You can find lecture notes, RISC-V as…
  ☆14Updated last year
• muhammedkocaoglu / mystic_riscv64
  64-bit RISC-V processor
  ☆14Updated 2 years ago
• eminfedar / rv32-im-cpu
  RISC-V RV32IM cpu circuit in Logisim Evolution.
  ☆27Updated 3 years ago
• yusfux / KASIRGA-GUN
  KASIRGA-GUN | RV32IMCX
  ☆11Updated 6 months ago
• mbaykenar / apis_anatolia
  "Mehmet Burak Aykenar" YouTube kanalında yayınlanan VHDL ve FPGA dersleri ile ilgili kodları içermektedir.
  ☆99Updated 8 months ago
• koraykarakurt / FPGA-from-Zero-to-Hero
  Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)
  ☆27Updated this week
• UCanLinux / riscv64-sample
  Building a busybox based RiscV 64-bit GNU/Linux system from scratch
  ☆50Updated 5 years ago
• mbaykenar / mpw7_yonga_soc
  Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C
  ☆15Updated 2 years ago
• sudhamshu091 / Single-Cycle-Risc-Processor-32-bit-Verilog
  Single Cycle RISC MIPS Processor
  ☆32Updated 3 years ago
• ensariskin / 5-Stage-Pipeline-RV32I
  5 Stage Pipelined RISC V Processor Design for RV32I Instruction Set
  ☆9Updated 2 years ago
• kerimturak / tcore-rv32imc
  ☆12Updated this week
• kirbyydoge / kasirga_2023
  Kasırga Sayısal Görüntü İşleme Kategorisi Hızlandırıcı Tasarımı
  ☆12Updated last year
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆112Updated 5 years ago
• merldsu / RISCV_Pipeline_Core
  This repository contains the design files of RISC-V Pipeline Core
  ☆35Updated last year
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆58Updated 2 months ago
• kirbyydoge / kasirga_gok_2023
  Kasırga - Gök Sayısal İşlemci Kategorisi RISC-V İşlemci Tasarımı
  ☆14Updated last year
• muhammedkocaoglu / SystemVerilog-Tutorials
  SystemVerilog derslerinde yazdığım kodları içermektedir.
  ☆13Updated last year
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆80Updated last year
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆16Updated last year
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆21Updated last year
• vinayrayapati / rv32i
  Implementation of RISC-V RV32I
  ☆17Updated 2 years ago
• aasthadave9 / Advanced-Physical-Design-Using-OpenLANE-Sky130
  This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…
  ☆15Updated 3 years ago
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆38Updated last year
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆61Updated 5 years ago
• KASIRGA-KIZIL / tekno-kizil
  KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
  ☆147Updated last year
• A-T-Kristensen / simple-alu-uvm
  This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit
  ☆22Updated 6 years ago
• yavuz650 / RISC-V
  Repository for Hornet RISC-V Core
  ☆18Updated 2 years ago
• AngeloJacobo / FPGA_OV7670_Camera_Interface
  Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
  ☆58Updated 3 years ago