Alternatives and similar repositories for fedar-e1-rv32i

Users that are interested in fedar-e1-rv32i are comparing it to the libraries listed below

• eminfedar / fedar-f1-rv64im
  5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.
  ☆214Updated 4 years ago
• necaticakaci / matrak
  Matrak Verilog ile yazılmış bir RISC-V işlemcidir.
  ☆11Updated last year
• TUTEL-TUBITAK / TEKNOFEST_2023_Cip_Tasarim_Yarismasi
  Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…
  ☆20Updated 2 years ago
• muhammedkocaoglu / mystic_riscv64
  64-bit RISC-V processor
  ☆16Updated 3 years ago
• yusfux / KASIRGA-GUN
  KASIRGA-GUN | RV32IMCX
  ☆11Updated last year
• eminfedar / rv32-im-cpu
  RISC-V RV32IM cpu circuit in Logisim Evolution.
  ☆27Updated 4 years ago
• kirbyydoge / kasirga_gok_2023
  Kasırga - Gök Sayısal İşlemci Kategorisi RISC-V İşlemci Tasarımı
  ☆17Updated 2 years ago
• mbaykenar / apis_anatolia
  "Mehmet Burak Aykenar" YouTube kanalında yayınlanan VHDL ve FPGA dersleri ile ilgili kodları içermektedir.
  ☆112Updated last year
• mbaykenar / computer-architecture
  This course is given in ERCIYES UNIVERSITY for Spring 2022-2023 semester as a fourth grade lecture. You can find lecture notes, RISC-V as…
  ☆18Updated 2 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆163Updated 6 years ago
• UCanLinux / riscv64-sample
  Building a busybox based RiscV 64-bit GNU/Linux system from scratch
  ☆52Updated 6 years ago
• mbaykenar / mpw7_yonga_soc
  Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C
  ☆20Updated 3 years ago
• koraykarakurt / FPGA-from-Zero-to-Hero
  Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)
  ☆36Updated 5 months ago
• muhammedkocaoglu / SystemVerilog-Tutorials
  SystemVerilog derslerinde yazdığım kodları içermektedir.
  ☆15Updated 2 years ago
• ensariskin / 5-Stage-Pipeline-RV32I
  5 Stage Pipelined RISC V Processor Design for RV32I Instruction Set
  ☆10Updated 3 years ago
• kirbyydoge / kasirga_2023
  Kasırga Sayısal Görüntü İşleme Kategorisi Hızlandırıcı Tasarımı
  ☆14Updated 2 years ago
• vinayrayapati / rv32i
  Implementation of RISC-V RV32I
  ☆27Updated 3 years ago
• martinKindall / risc-v-single-cycle
  A Single Cycle Risc-V 32 bit CPU
  ☆57Updated 3 weeks ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆144Updated 6 years ago
• KASIRGA-KIZIL / tekno-kizil
  KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
  ☆154Updated 2 years ago
• JAYRAM711 / 100-DAYS-OF-RTL
  This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…
  ☆20Updated 2 years ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆151Updated 5 years ago
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆129Updated 2 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆118Updated 2 years ago
• yathAg / openroad_vsd_7nmContest
  ☆15Updated 2 years ago
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆38Updated 3 years ago
• iamrk-vlsi / RISC-V-MYTH-Workshop
  5 days (30 hours) is all what took me to learn the basics and design a pipelined RV32I core. Check this article to know more !
  ☆12Updated 3 years ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆186Updated last month
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆57Updated last year
• baselkelziye / PCIe_Scrambler
  PCIe GEN1, GEN2 and GEN3 Scrambler, This Scrambler is able to scramble 1,2 and 4 bytes of data in 1 clock cycle in respect to the scrambl…
  ☆14Updated 6 months ago